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Multiple clock synthesizer
| Details |
Inventors: McDermott, Bruce C.;
Assignee: Eastman Kodak Company (Rochester, NY)
Primary Examiner: Callahan; Timothy P.
Assistant Examiner:
Attorney, Agent or Firm: Dugas; Edward
The synthesizer of the present invention is a multiple clock synthesizer for generating multiple clock signals with improved clock width and position accuracy. Within the synthesizer an oscillator provides a train of pulses corresponding to a base signal. A plurality of delay devices, formed of differing lengths of cables, are coupled to the oscillator with each cable providing a different delay to the train of pulses to in turn provide a plurality of delayed clocking signals. A plurality of registers, each having, a clocking input, a plurality of output taps, and load inputs and corresponding in number to the plurality of delay devices receive on their clocking inputs a delayed clocking signal from an associated one of the plurality of delay devices. A binary number is circulated in each of the plurality of registers as a function of the associated clocking signal to provide at their outputs a sequence of pulses each having a leading edge displacement defined by 1 divided by the number of outputs from the plurality of delay devices, times the number of outputs per register, times the element clock period. The number of outputs in the clock delay section corresponding to the number of register used. |
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DETAILED DESCRIPTION In a preferred embodiment of the invention, there is provided a multiple clock synthesizer having an oscillator for providing a train of pulses corresponding to a base signal along with a plurality of delay devices coupled to said oscillator means each providing a different delay to said base signal to provide a plurality of delayed clocking signals and a plurality of registers each having, a clocking input, a plurality of output taps, and loading inputs and corresponding in number to the plurality of delay devices each of the registers receiving on its clocking input a delayed clocking signal from an associated one of the plurality of delay devices, and on it loading inputs a binary number which is circulated in each of the plurality of register means as a function of the associated clocking signal to provide at the output taps a sequence of pulses each having a leading edge displaced by an increment of time corresponding to one divided by the number of shift registers times the number of output taps per register times the element clock period.
From the foregoing, it can be seen that it is a primary object of the present invention to provide an improved architecture for synthesizing high resolution and high accuracy clocks.
It is another object of the present invention to provide a multiple clock synthesizer architecture having low cost and power consumption.
It is yet another object of the present invention to provide a multiple clock synthesizer architecture that has a digital resolution defined as a function of the number of outputs in the clock delay section, times the number of shift registers, and the number of outputs per shift register.
Another object of the present invention is to provide a clock synthesizer having selectable, synchronous outputs for clock waveform construction.
These and other objects of the present invention will become more apparent when taken in conjunction with the following description and drawings, wherein like characters indicate like parts and which drawings form a part of the present disclosure
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