DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Referring to FIG.
9A, a sigma-delta A/D converter in accordance with the invention has four sigma-delta modulators 101, 102, 103, 104 in parallel which have their outputs Q1, Q2, Q3, Q4 multiplexed together through a multiplexor circuit 105 and passed through a digital low pass filter circuit 106.
Each of the modulators is implemented as a second-order sigma-delta modulator of the switched capacitor type, as previously described with respect to FIGS.
6, 7A, 7B, and 8.
Each modulator stage is provided with the analog input signal to Vin and a modulator clock CLK1, CLK2, CLK3, CLK4, respectively.
The analog input signal is sampled by all four second-order modulators.
Clocks are generated such that the master clock CLK is four times faster than the modulator clocks CLK1, CLK2, CLK3, CLK4.
In one version, the modulator clocks are staggered in phased sequence over time.
Thus, the output of each modulator will appear as the signal processing is done on a different part of the signal, i.
e.
, the signal is sampled every fourth master clock cycle respectively for each modulator.
The outputs Q1, Q2, Q3, Q4 of the modulators are sampled by the multiplexor, via multiplexor clocks CLKM1, CLKM2, CLKM3, CLKM4, so that the overall output Q appears to have a data rate of the master clock CLK and all the modulator outputs are combined in correct phase sequence.
In FIG.
9B, one such sigma-delta modulator stage is shown implemented in MOS technology.
The transmission gates for the integrators are NMOS and PMOS having drain and source coupled together.
The NMOS gate is driven by the modulator clock CLKi, and the gate of the PMOS gate is driven by the complementary clock CLKB.
Bias circuitry is not shown as there are several commonly known circuits for properly biasing operational amplifiers and comparators.
The clock generator circuitry is not shown as the generation of correct timing control signals is well known to those versed in digital logic.
In FIG.
10, the timing of the master clock CLK, modulator clocks CLK1, CLK2, CLK3, CLK4, multiplexor clocks CLKM1, CLKM2, CLKM3, CLKM4, modulator outputs Q1, Q2, Q3, Q4, and combined overall output Q are shown
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Multiplexer-related 
