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Parallel data bus integrated clocking and control
| Details |
Inventors: Hogeboom, John Gordon;
Assignee: Nortel Networks Limited (Montreal, CA)
Primary Examiner: Chin; Wellington
Assistant Examiner: Duong; Frank
Attorney, Agent or Firm: Smart & Biggar, Donnelly; Victoria
A data bus is provided having both a synchronous clock and a channel of data control information integrated in a single signal path. For a data bus having a particular bit time, the integrated clock and control signal has a clock high and low time in units equal to one bit time. One edge of the integrated clock and control signal is fixed in phase for bit timing, the alternate edge is phase-modulated. The phase-modulated clock edge carries framing and control data. The fixed-phase bit-timing edge regulates a DLL or PLL to extend the timing. The clock rate is preferably chosen to be equal to the multiplexing cycle rate of multiplexed data carried on the parallel bus. |
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DETAILED DESCRIPTION A clock is always needed with transmitted data in order to define the position of individual bits in the data sequences.
If the clock is directly transmitted, such a clock signal may require special handling, e.
g.
, the use of higher-speed interfaces than those used by the data channels.
In this invention the clock signal is transmitted at a lower rate, and only a primary edge (for example, the falling edge) is used to control the timing of a PLL or DLL, which can then regenerate all required equal- or higher-rate clocks with required stability and phase relations.
By using only timing increments of one bit time for the clock signal high and low periods, the same transmission media and interfaces may be used for the clock as are normally used for the associated data stream or streams.
Furthermore, the alternate edge of the signal is independently modulated in increments of one data bit time to carry control data.
Control data transmitted in this way, integrated with the clock signal, may be used for any purpose, including specific low-speed timing purposes often called framing.
At the same time, and in the same manner, such control data can be used in a process of adjusting or "trimming" delays of data from two or more sources multiplexed onto a data line.
At the receiving end of the bus, the delays are adjusted in accordance with the control data, so that the various multiplexed data streams will align with each other in time at data receivers used to recover the bit streams.
One clock signal may be used in these ways for many parallel data lines, which may differ from one another, and which may also require unique timing settings.
The clock signal is an ideal signal to carry such control data, since it must already connect to all transmitters and receivers, and because it directly provides the timing information needed to optimally recover the data it carries.
Thus, a data bus is provided having both a synchronous clock and a channel of data control information integrated in a single signal path
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Multiplexer-related 
