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Details
Inventors: Gersbach, John E.; Novof, Ilya I.;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Kuntz; Curtis
Assistant Examiner: Webster; Bryan E.
Attorney, Agent or Firm: Calfee, Halter & Griswold

A phase lock logic system is provided for (i) determining differences in phase and frequency of a received composite clock and data signal with respect to a local clock signal and (ii) providing control signals to enable accurate sampling and reconstruction of the received data. The system includes a delay element which outputs a plurality of phase-delayed signals each being incrementally shifted in phase from the local clock signal. A sorting circuit receives the phase-delayed local clock signals and the incoming composite signal, defines a number of time intervals in each cycle of the local clock signal equal to the number of phase-delayed local clock signals, and sorts positive and negative going transitions in the received composite signal into the defined time intervals. Counters indicate the number of transitions occurring during a selected time interval. A logic circuit reads the counters, determines the differences in frequency and phase of the received composite signal with respect to the local clock signal, and outputs first and second control signals. A barrel shifter responsive to the first control signal selects which of the counters counts the number of transitions occurring in a given time interval. A multiplexer responsive to the first and second control signals extracts the phase-delayed local clock signal which most closely approximates the phase and frequency of the received composite signal. A regenerator compares the extracted signal to the received composite signal and outputs regenerated data.

DETAILED DESCRIPTION According to the present invention, a phase lock logic system is provided for determining (i) the delay or phase shift of a received composite signal with respect to a local clock signal and (ii) the difference in frequency between the received signal and local clock signals.
Based on these determinations, a logic circuit issues control signals to enable accurate sampling and reconstruction of the originally transmitted data.
The system is suitable for high speed applications and can be realized in hardware or in hardware/software combination.
The local clock signal operates at a phase and frequency which are slightly mismatched to the phase and frequency of the received composite signal.
The local clock signal is divided by a delay element which outputs a plurality n of phase-delayed signals of the same frequency as the local clock signal.
The sum of the delays of n phase-delayed signals corresponds to the period of the local clock signal.
Each of these delayed signals is thus incrementally shifted in time about 1/n of a local clock signal period.
A data edge sorting circuit receives each of the n phase-delayed local clock signals and establishes n time intervals per local clock signal period.
The sorting circuit also receives the incoming composite signal, senses the positive and negative going transitions of pulses in the incoming signal, and sorts these positive and negative going transitions into the n time intervals.
The output of the sorting circuit thus provides an indication of the time intervals during which the data transitions occur, and the phase shift of these transitions with respect to corresponding positive and negative going transitions in the local clock signal.
A series of counters counts the number of positive and negative going transitions occurring during the established time intervals into which the local clock signal period is divided and stores this information.
The counters associated with each of the n equal time intervals thereby provide a real time history of the time of transitions in the received composite signal



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