Phase detection circuit for stepwise measurement of a phase relation

DETAILED DESCRIPTION It is an object of the invention to provide an accurate phase detection circuit comprising few circuit elements and operating unambiguously.
According to the invention, a phase detection circuit of the type described in the opening paragraph is therefore characterized in that the logic circuit includes a group of gate circuits alternately having an AND and a NOR function or a NAND and an OR function arranged each time between similar outputs of two successive memory elements and in that the measuring circuit comprises two EXCLUSIVE-OR gate circuits each being coupled to a pair of outputs of the delay circuit and having their outputs coupled to a control circuit for controlling the delay time of the delay circuit in such a way that it corresponds to the period of the first clock signal.
Using a control circuit for the delay time of the delay circuit in such a way that it corresponds to the period of the first clock signal provides the possibility of omitting the further memory elements, while the number of indicated gate circuits and the number of memory elements are now only determined by the number of steps that must be detected instead of by the desired accuracy.
The indicated gate circuits further ensure an unambiguous determination of the phase relation between the two clock signals without additional measures being required in transitions between two successive steps.
A favorable application of the phase detection circuit is, for example, its use in a sampling frequency converter circuit in which a digitally decoded color television signal occurs at a sampling frequency of four times the chrominance sub-carrier frequency which is converted to a sampling frequency being a number of times the line frequency of the color television signal.
Each output of a gate circuit can then switch on a group of interpolation coefficients associated with the measured phase relation.