Phase-locked loop circuit and method

DETAILED DESCRIPTION OF THE INVENTION Referring now to the drawings, FIG.
1 shows a block diagram of a first embodiment of the present invention.
The principal components of the phase-locked loop (PLL) circuit include a phase detector 10, followed by a low pass filter 12.
The output of filter 12 is an input to a voltage controlled oscillator (VCO) 14 and the output of VCO 14 is fed back to one of the phase detector 10 inputs by way of a programmable frequency divider 16.
Divider 16 is controlled by control logic 18.
The external (input) clock EC is connected to one input of phase detector 10.
The remaining input of detector 10 receives an internal clock IC which is produced by the PLL circuit.
Clock IC has a fixed phase relationship with the external clock EC.
The objective of the FIG.
1 circuit is to limit the skew between the external and internal clocks to a well controlled minimum value over a wide range of external clock EC frequencies.
The output V.
sub.
d of the phase detector 10 is a function of the phase difference between the two clocks, as follows (the following equation and the other equations disclosed herein are only linear approximations of a phase-locked loop): V.
sub.
d =K.
sub.
d (.
phi.
.
sub.
x -.
phi.
.
sub.
o) (1) where V.
sub.
d is the output of the phase detector; K.
sub.
d is the gain of the phase detector 10; .
phi.
.
sub.
x is the phase of the external clock EC; and .
phi.
.
sub.
o is the phase of the internal clock IC.
The output of the low pass filter 12 is a voltage V.
sub.
c and is as follows: V.
sub.
c =F(s) V.
sub.
d (2) where V.
sub.
c is the output of the filter; V.
sub.
d is the input to the filter; and F(s) is the transfer function of the filter.
The output CL.
sub.
I of the voltage controlled oscillator (VCO) 14 has a frequency f.
sub.
i and phase .
phi.
.
sub.
i which depend upon the magnitude of control voltage V.
sub.
c.
The phase of output CL.
sub.
I may be expressed as follows: .
phi.
.
sub.
i =K.
sub.
c V.
sub.
c /s (3) where .
phi.
.
sub.
i is the phase of output CL.
sub.
I ; K.
sub.
c is the gain of the VCO; and s is the Laplace transform variable