Phase-locked loop or delay-locked loop circuitry for programmable logic devices

DETAILED DESCRIPTION These and other objects of the invention are accomplished in accordance with the principles of the invention by providing PLL or DLL circuitry on a programmable logic device in which the feedback loop of the PLL or DLL is constructed to substantially parallel and duplicate at least a portion of the clock signal distribution network that receives the clock signal manipulated by the PLL or DLL.
In this way the feedback Loop of the PLL or DLL is subject to substantially the same distributed propagation delay effects as the clock signal distribution network receiving the clock signal modified by the PLL or DLL.
This increases the accuracy with which the PLL or DLL circuitry emulates delay in the clock signal distribution network.
Moreover, emulation accuracy is maintained despite variations due to fabrication process, temperature, power supply voltage, and even changes in circuit scale.
The signal propagating in the above-described distributed feedback loop of the PLL or DLL circuitry may be slightly shifted in time (preferably by a programmable selectable amount) relative to the signal in the clock signal distribution network.
In this way one PLL or DLL can provide two different clock signals, each of which has an accurate phase relationship to an input clock signal applied to the programmable logic device.
One of these signals can be used to clock input, output, or input/output (generically "I/O") registers of the programmable logic device.
The other of these signals can be used as an output clock signal of the programmable logic device.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.