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Programmable down-sampler having plural decimators and modulator using same
| Details |
Inventors: Huang, Ke-Chiang;
Assignee: Industrial Technology Research Institute (Hsinchu, TW)
Primary Examiner: Grimm; Siegfried H.
Assistant Examiner:
Attorney, Agent or Firm: Christensen O'Connor Johnson & Kindness PLLC
A digital QPSK demodulator includes a plurality of two-input-two-output (TITO) two-fold decimators where each TITO two-fold decimator operates at a rate equal to its input data rate. The in-phase I signal and the quadrature Q signal are computed in an interleaved sequence of {Q"(n), I"(n), Q"(n+1), I"(n+1), . . . } to generate Q" decimation output and I" decimation output. The TITO two-fold decimators are cascaded in a reverse order to form a programmable down-sampler which decimates the input data by factors of 1, 2, 4, 8 or more. In a first embodiment, the programmable down-sampler is coupled between a complex multiplier and an interpolator. In a second embodiment, the in-phase and quadrature signals are fed through a complex multiplier, an interpolator, then the programmable down-sampler. In the third embodiment, the in-phase and quadrature signals are fed through an interpolator, a complex multiplier, then the programmable down-sampler. |
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DETAILED DESCRIPTION The present invention discloses a programmable down-sampler, comprising (1) a first mux having a pair of first inputs for receiving a first input signal and a second input signal, a pair of second inputs, a control input, a pair of outputs for generating a decimated quadrature output signal and a decimated in-phase output signal; (2) a first two-fold decimator having a pair of outputs coupled to the pair of second inputs of the first mux and having a pair inputs; (3) a second mux having a pair of first inputs for receiving the first input signal and the second input signal, a pair of second inputs, a control input, a pair of outputs coupled to the pair of inputs of the first two-fold decimator; (4) a second two-fold decimator having a pair of outputs coupled to the pair of second inputs of the second mux and having a pair of inputs; wherein a first control signal is coupled to the control input of the first mux to activate the pair of first inputs of the first mux for routing the first input signal and the second input signal directly to the pair of outputs of the first mux if no decimation is desired, a second control signal being coupled to the control input of the second mux to activate the pair of first inputs of the second mux for receiving the first input signal and the second input signal and the first control signal activating the pair of second inputs of the first mux which coupled to the pair of outputs of the first two-fold decimator if a decimation by a factor of 2 is desired.
A core processor for computing a two-input-two-output two-fold decimation operates at the same rate as the decimation input rate R.
The decimations of the in-phase I signal and the quadrature Q signal are computed in an interleaved sequence of {Q"(n), I"(n), Q"(n+1), I"(n+1), .
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} to generate output Q" signal and output I" signal.
The programmable down-sampler contains a plurality of two-fold decimators cascaded in series arranged in a reverse order.
The decimation by a factor 2
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Multiplexer-related 
