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Low power, slew rate insensitive power-on reset circuit |
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Programmable voltage controlled ring oscillator |
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Symmetrical waveform signal generator having coherent frequency shift capability |
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Constant duty cycle, frequency programmable clock generator |
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Peripheral control circuitry for personal computer |
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Programmable frequency divider |
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Variable frequency clock pulse generator for microcomputer |
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Programmable multiphase clock divider |
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Scheduling mechanism for network adapter to minimize latency and guarantee background processing time
| Details |
Inventors: Ramakrishnan, Kadangode K.; Sawyer, David; Weeks, Phillip J.; Washabaugh, Douglas M.;
Assignee: Digital Equipment Corp. (Maynard, MA)
Primary Examiner: Harvey; Jack B.
Assistant Examiner: Auve; Glenn A.
Attorney, Agent or Firm: Johnston; A. Sidney, Kuta; Christine M.
Method and apparatus for scheduling operations of a network adapter in such a way as to minimize latency in processing received data packets, while still guaranteeing time for processing necessary background tasks. The method includes executing a polling loop in which repeated tests are made for the presence of receive data to process, but only a limited amount of receive data processing is performed before checking for background processing that needs to be performed. The polling loop ensures that immediate attention is given to processing of receive data, without the inherent latency of interrupt processing, but still gives periodic opportunities for background processing. Background processing is performed for a guaranteed minimum processing time before permitting a return to receive processing. Background processing may be performed without a guaranteed minimum processing time, but only when there is currently no receive processing to do. |
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DETAILED DESCRIPTION The present invention resides in a network adapter scheduling method, and corresponding apparatus, in which a polling loop includes receive data processing, and checking for background processing tasks. Briefly, and in general terms, the method of the invention comprises the steps of executing a polling loop, including checking for receive processing to do, performing a limited amount of any receive processing that needs to be performed, and then identifying any background processing tasks that need to be performed; and executing the background processing tasks, if any are identified in the polling loop. A minimum background processing execution time is guaranteed (for background tasks) before a return is made to the ongoing receive processing. The method includes the step of returning to the polling loop no later than upon expiration of the minimum background processing time. In the method of invention, latency in processing any receive data is minimized by eliminating the overhead associated with an interrupt on receiving a packet of data, while still guaranteeing processing time for necessary background tasks. More specifically, the step of identifying background tasks includes checking for the presence of tasks already in progress, and checking for the occurrence of timer interrupts pending and to be dealt with. These checking steps are performed after performing a selected and limited amount of receive data processing, such as by processing a selected number of data buffers. Since the time for this limited amount of processing is known fairly accurately, the occurrence of timer interrupts that are pending can be checked for on a regular and frequent basis, without the inherent overhead of interrupt processing routines. The need for "timer interrupts" is to deal with those cases when there are no packet buffers processed for some time. If the adapter was busy all the time, these timer interrupt events would be checked without the need for hardware interrupts. The step of identifying background tasks may also include counting the number of receive buffers processed, to determine the time at which this identification is performed
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