Semiconductor memory device including address transition detecting circuit

DETAILED DESCRIPTION One object of the present invention is to reduce a consumed current in writing operation in a semiconductor memory device including an ATD generating circuit.
Another object of the present invention is to enable a main amplifier circuit to take written data without activating an ATD generating circuit and a preamplifier circuit in writing operation in a dynamic random access memory.
A semiconductor memory device according to the present invention includes a memory circuit for storing data, an address signal input circuit, a data bus, an input buffer circuit, an amplifier circuit, an address transition detecting circuit, a first control circuit and a second control circuit.
The address signal input circuit receives an externally applied address signal.
The data bus transmits data to be written in the address of the memory circuit designated by the address signal, or data read from the address of the memory circuit designated by the address signal.
The input buffer circuit receives externally applied data, and applies the same to the data bus.
The amplifier circuit amplifies and holds the data read onto the data bus.
The address transition detecting circuit detects transition of the address signal from the address signal input circuit to generate a detection signal.
The first control circuit activates the amplifier circuit in response to the detection signal from the address transition detecting circuit in reading operation.
The second control circuit activates the input buffer circuit and further activates the amplifier circuit in writing operation.
The second control circuit first generates a first write control signal, and thereafter generates a second write control signal in writing operation.
The first control circuit responds to the detection signal to generate an output control signal.
The input buffer circuit is activated in response to the first write control signal.
The amplifier circuit is activated in response to the second write control signal or the output control signal