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| Multiple clock synthesizer |
| In a preferred embodiment of the invention, there is provided a multiple clock synthesizer having ... |
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| Phase and frequency adjustable digital phase lock logic system |
| According to the present invention, a phase lock logic system is provided for determining (i) the ... |
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| Digital phase alignment and integrated multichannel transceiver employing same |
| We claim: 1. A synchronizer for phase aligning an input signal, having a data transition, with a ... |
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| Spread spectrum communication apparatus |
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| Advanced technology anti-G suit |
| Referring now to FIG. 1 of the drawings, there is shown a simplified perspective view of an anti-G ... |
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| Multiple satellite repeater capacity loading with multiple spread spectrum gateway antennas |
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Start-stop synchronous communication speed detecting apparatus
| Details |
Inventors: Hiraguchi, Masayoshi; Hattori, Masanori;
Assignee: NEC Corporation (JP)
Primary Examiner: Heyman; John S.
Assistant Examiner:
Attorney, Agent or Firm: Ostrolenk, Faber, Gerb & Soffen
A start-stop synchronous communication speed detecting apparatus includes a counter, a speed determining unit, a clock switching unit, a shift register, a character determining unit, a code generator, and a controller. The counter counts a time period, in which received data is a space polarity, in start-stop synchronous communication. The speed determining unit compares the count value with a time per bit of a specified communication speed. The clock switching unit selects a clock synchronized with the start bit of the received data and having the same frequency as that of the specified communication speed. The shift register stores the received data. The character determining unit compares a received character from the register with a predetermined character. The code generator supplies codes of the first to Nth characters to the character determining unit. The controller counts received characters by the output clocks from the switching unit and informs the generator of the number of characters, generates a reception completion information signal upon receiving a predetermined character string without any abnormality, and outputs a signal for initializing the counter by a signal indicating abnormality in the speed and character determining units. |
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DETAILED DESCRIPTION It is an object of the present invention to provide a start-stop synchronous communication speed detecting apparatus capable of detecting a communication speed without performing any software processing, thereby increasing an operating ratio in other operations of a CPU.
It is another object of the present invention to provide a start-stop synchronous communication speed detecting apparatus capable of detecting a communication speed even if the communication speed is high.
In order to achieve the above objects of the present invention, there is provided a start-stop synchronous communication speed detecting apparatus comprising a counter for counting a time period, in which received data is a space polarity, in start-stop synchronous communication, speed determining means for comparing the count value with a time per bit of a specified communication speed, clock switching means for selecting a clock synchronized with the start bit of the received data and having the same frequency as that of the specified communication speed, a shift register for storing the received data, character determining means for comparing a received character from the shift register with a predetermined character, code generating means for supplying codes of the first to Nth characters to the character determining means, and a controller for counting received characters by the output clocks from the clock switching means and informing the code generating means of the number of characters, generating a reception completion information signal upon receiving a predetermined character string without any abnormality, and outputting a signal for initializing the counter by a signal indicating abnormality in the speed determining means and the character determining means.
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Multiplexer-related 
