System and method for alleviating skew in a bus

DETAILED DESCRIPTION The present invention provides a most signal skew tolerant timing window for signal transfer in relation to the capture clock timing.
The teaching of this invention is to align the signal of each signal line, through delay insertion, to the most skew tolerant timing window basing upon repeatedly sampling of signal timing of each signal line.
Such an alignment will significantly improve the signal bus data capture capability and consequently reduce the data transfer cycle time for multiple bits data transfer.
The present invention involves inserting a delay adjuster between the receiver and the latches associated with each bus line.
The purpose of the delay adjuster is to insert delay to each path so that the signal arrives at the capture latch in the most favorable condition (skew tolerant wise).
To calibrate the delay of each signal path, a timing digitizer is used.
The timing digitizer may be an 8-6 bit shift register cell.
The shift register cell is triggered by a clock with a frequency 4.
times.
that of the CPU frequency.
The timing digitizer is placed subsequent to the timing adjuster.
To determine the timing relationship between the clock and the incoming signal, an ideal signal window generated by the local clock is also fed into another timing digitizer.
All shift register cells for the timing digitizers are tied together as a scan chain to be scanned out and passed on to a service processor which compares the delay of each signal path with an idea signal window and subsequently inserts delay using the timing adjusters to particular bus lines.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood.
Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.