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| Programmable voltage controlled ring oscillator |
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| Symmetrical waveform signal generator having coherent frequency shift capability |
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| Constant duty cycle, frequency programmable clock generator |
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| Peripheral control circuitry for personal computer |
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| Programmable frequency divider |
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| Variable frequency clock pulse generator for microcomputer |
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| Programmable multiphase clock divider |
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System for transferring portion of data to host from buffer if size of packet is greater than first threshold value but less than second threshold value
| Details |
Inventors: Cedros, Craig; Yaple, Nelson; Chalupsky, Dave; Martin, Phil;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Lee; Thomas C.
Assistant Examiner: Perveen; Rehana
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman
A method and apparatus to optimize buffer memory management in a computer system communications resource. The present invention decreases the time for receiving data from and transmitting data to a network by providing for receipt and transmittal of a data packet, prior to the data packet being in a communications resource buffer memory. Consequently, data spends less time in the communications resource buffer memory. This allows a communications resource to handle more data without increasing the size of its buffer memory and to increase the effective data transfer rate. The present invention provides a means for: 1) starting the transmission of data into the network before all data has been transferred to buffer memory in the communications resource, 2) beginning the transfer of data from the buffer memory of the communications resource before the complete data packet has been received and stored in buffer memory, and 3) error checking to insure data integrity. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A method and apparatus for optimization of buffer memory management in a communications resource is described.
In the following description, numerous specific details are set forth such as the timing of data signals in order to provide a thorough understanding of the present invention.
It will be apparent, however, to one skilled in the art that the present invention may be practiced without such specific details.
In other instances, specific implementation details such as the physical interface to the Local Area Network (LAN) media or a CPU bus have not been shown in detail in order not to unnecessarily obscure the present invention.
While the communications resource of the currently preferred embodiment of the present invention is implemented as a LAN interface adapter supported by a general purpose computer, it would be apparent to one skilled in the art to embody the present invention in a fixed function system, e.
g.
an X-Terminal.
Further, the present invention may be embodied as an adapter to couple to a computer system into any type of environment where processing systems are in communication, e.
g.
a parallel processing system.
Such embodiments would not depart from the spirit and scope of the present invention.
The computer system 100 of the currently preferred embodiment is described with reference to FIG.
1.
A computer system as may be utilized by the preferred embodiment generally comprises a bus structure or other communication means 101 for communicating information between the various components of the computer system, a processor means 102 coupled with said bus 101 for processing information, a random access memory (RAM) or other storage device 103 (commonly referred to as a main memory) coupled with said bus 101 for storing information and instructions for said processor 102, a read only memory (ROM) or other static storage device 104 coupled with said bus 101 for storing static information and instructions for said processor 102, a display monitor 105 is coupled with said bus 101 for communication with the processor 102, a data storage device 106, such as a magnetic disk or disk drive, coupled with said bus 101 for storing information and instructions, an alphanumeric input device 107 including alphanumeric and other keys coupled to said bus 101 for communicating information and command selections to said processor 102, a cursor control device 108, such as a mouse, track-ball, cursor control keys, etc
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Multiplexer-related 
