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Timing recovery system for a digital signal processor
| Details |
Inventors: Knutson, Paul Gothard; Ramaswamy, Kumar; McNeely, David Lowell;
Assignee: Thomson Consumer Electronics, Inc. (Indianapolis, IN)
Primary Examiner: Tse; Young T.
Assistant Examiner:
Attorney, Agent or Firm: Tripoli; Joseph S., Herrmann; Eric P., Kurdyla; Ronald H.
A timing recovery system for a digital signal receiver receives a signal, representing successive symbols, from a transmitter. The symbols are subject to exhibiting multiple symbol rates. The system derives a sample enable signal from the received input signal and employs a single, fixed frequency oscillator. A source of samples representing the received signal are sampled at a fixed frequency. An interpolator is coupled to the sample source and is responsive to a control signal. The interpolator produces samples taken at times synchronized to the successive symbols from the transmitter. A phase error detector is coupled to the interpolator, detects a phase error between the sample times of the transmitter synchronized samples produced by the interpolator and times of the successive transmitter symbols, and supplies a phase error signal. The phase error signal is coupled to one input terminal of a summer and a source of a nominal delay signal is coupled to the other. A numerically controlled delay produces the control signal for the interpolator in response to the signal from the summer. An output signal from the interpolator is filtered by a fixed, non-adaptive pulse-shaping filter. |
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DETAILED DESCRIPTION In accordance with principles of the present invention, a timing recovery system for a digital signal receiver, receives a signal, representing successive symbols, from a transmitter.
An interpolator, coupled to the symbol source, responds to a control signal for producing samples taken at times synchronized to the successive symbols from the transmitter.
A control network which provides the control signal includes a controlled delay network responsive to an output signal from said interpolator and to a nominal delay offset signal.
More specifically, the system comprises a source of samples representing the received signal, the samples taken at a fixed frequency.
An interpolator is coupled to the sample source and is responsive to a control signal.
The interpolator produces samples taken at times synchronized to the successive symbols from the transmitter.
A phase error detector is coupled to the interpolator, detects a phase error between the sample times of the transmitter synchronized samples produced by the interpolator and times of the successive transmitter symbols, and supplies a phase error signal.
The phase error signal is coupled to one input terminal of a summer and a source of a nominal delay signal is coupled to the other.
A numerically controlled delay produces the control signal for the interpolator in response to the signal from the summer.
A timing recovery system according to the present invention operates by initially sampling the received signal at a fixed frequency slightly higher than twice the highest desired transmitter symbol rate.
This initially sampled signal is then processed by an interpolator to generate a sequence of samples synchronized to the transmitter symbol rate.
These synchronized samples are supplied to a digital phase error detector.
The output of the digital phase error detector is supplied to a second order loop filter.
A predetermined value, representing a desired nominal sampling time delay, is added to the output signal of the loop filter
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