Delay time estimation method and recording medium storing estimation program

DETAILED DESCRIPTION Accordingly, a general object of the present invention is to provide a delay time estimation method and a recording medium storing an estimation program in which the aforementioned disadvantages are eliminated.
Another and more specific object of the present invention is provide a precise delay time estimation method and a recording medium storing an estimation program in which a saturation region, characterized by a gradual decrease in current, is represented so that delay time estimation that matches the transistor characteristic.
The aforementioned objects can be achieved by a delay time estimation method for estimating a delay time in a logic circuit that includes a MOS transistor, comprising the steps of: modeling the MOS transistor by a resistive element having fixed resistance and a power source voltage that varies with time; and segmenting an operating characteristic of the MOS transistor thus modeled into a fist region in which a current increases as a gate potential varies, a second region corresponding to a saturation region of the MOS transistor in which region the current gradually decreases as the gate potential remains constant, and a third region corresponding to a linearity region of the MOS transistor in which region the current decreases as the gate potential remains constant.
The delay time estimation method may be adapted for a circuit in-which a plurality of logic circuits that includes MOS transistors and comprise the steps of: segmenting an operating characteristic of last-stage MOS transistor constituting a logic circuit of a last stage into a first region in which a current increases as a gate potential varies, a second region corresponding to a saturation region of the last-stage MOS transistor in which region the current gradually decreases as a gate potential remains constant and a third region corresponding to a linearity region of the last-stage MOS transistor in which region the current decreases as the gate potential remains constant