Integrated waveshaping circuit using weighted current summing

DETAILED DESCRIPTION In accordance with the present invention, a waveshaping circuit for generating an output data signal and a complementary output data signal in response to a input data signal, a delayed input data signal, and an oscillator signal is disclosed.
The present invention reduces radiated emissions and increases circuit board space by providing the functionality of the external summing resistor network and the external filter in a waveshaping circuit which can be packaged as a single integrated circuit.
The waveshaping circuit includes a phase-lock-loop stage that generates a plurality of incrementally-delayed timing signals in response to the oscillator signal.
The plurality of incrementally-delayed timing signals can be formed, for example, by feeding the oscillator signal into a series of inverter gates which are controlled to have a substantially equivalent propagation delay between each inverter gate.
The waveshaping circuit further includes an input logic stage that generates a plurality of pairs of logic signals in response to the plurality of incrementally-delayed timing signals.
Each timing signal generates one corresponding pair of logic signals by periodically latching the input data signal so that a logic state and an inverse logic state of the input data signal are simultaneously provided by the corresponding pair of logic signals.
The waveshaping circuit also includes a delayed input logic stage that generates a plurality of pairs of delayed logic signals in response to the plurality of incrementally-delayed timing signals.
Each timing signal generates one corresponding pair of delayed logic signals by periodically latching the delayed input data signal so that a logic state and an inverse logic state of the delayed input data signal are simultaneously provided by the corresponding pair of delayed logic signals.
The plurality of pairs of delayed logic signals correspond to the plurality of pairs of logic signals so that each pair of delayed logic signals corresponds to one pair of logic signals