Method, apparatus and computer program product for implementing physical interconnect fault source identification

DETAILED DESCRIPTION Principal aspects of the present invention are to provide a method, apparatus and computer program product for implementing physical interconnect fault source identification.
Other important aspects of the present invention are to provide such method, apparatus and computer program product for implementing physical interconnect fault source identification substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method, apparatus and computer program product are provided for implementing physical interconnect fault source identification.
Interconnect test data are processed and each unique failing chip combination is identified.
Each common failing chip of the identified unique failing chip combinations is identified.
A high probability failure is reported for each identified common failing chip having a count value above a set threshold.
In accordance with features of the invention, a net naming algorithm is provided for assigning unique patterned names for all system nets.
Then redundant failing chip combinations are eliminated using the net naming algorithm.
A low probability failure is reported for each identified common failing chip having a count value less than or equal to the set threshold.
The high probability failure is reported for each said identified common failing chip having a count value greater than one.