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Processing system having a storage set with data designating operation state from operation states in instruction memory set with application specific block
| Details |
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Inventors: Iida, Kouichi;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Bowler; Alyssa H.
Assistant Examiner: Pan; Daniel H.
Attorney, Agent or Firm: Fay, Sharpe, Beall, Fagan, Minnich & McKee
The core DSP is extended to a functional module extension, for example having extended memory and input/output circuitry, which extended module is mapped in the address base of the data storage of the core DSP, whereby an ASIC-expanded LSI may be wholly formed on a single semiconductor substrate in an efficient manner. That is, the data transfer, address signals and control signals usable within the core with respect to the core memory are equally applicable to the extended module, so that the core DSP does not have to be re-evaluated and the core instruction sets and software are equally applicable without debugging, when the core DSP is extended for a specific application by adding an extension module. |
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DETAILED DESCRIPTION It is an object of the present invention to provide a DSP that is particularly applicable to ASIC, application specific integrated circuit, whereby the DSP may be adapted quickly to various specific applications in a more efficient manner than previously accomplished.
The present invention is related to studies made by the inventor on the technology for expanding a digital signal processor, DSP, used as an ASIC, in such a way that the fundamental circuit blocks necessary for the DSP are used as a core, that is repeatable without change for various different applications.
These studies have revealed that the prior art DSP has not given any consideration to expanding the DSP as an ASIC.
It is an object of the present invention to add a desired extending block around a core DSP, thereby to construct an entirely new DSP as a whole based upon a specific application, without redesigning the core DSP.
By way of an example, in the case of a digital processor of the type in which an internal data bus is not directly open to the exterior and is interfaced with the exterior through data transfer instructions for registers constituting a host interface portion, when it is intended to add a timer block and a parallel input/output circuit block, the instruction codes for coping with the new data transfer instructions must be added, without the present invention, for the transfer of data between the additional blocks and the existing internal blocks.
In consequence, the fundamental alternation of software for the instruction code set of the DSP must be accomplished, without the present invention, and a logic verification or test of the alteration and the new software debugging are required all on the scale of an entirely newly constructed DSP, without the present invention.
Therefore, the labor involved in developing a new LSI in spite of the addition of the partial input/output function, is very great, without the present invention.
Furthermore, when constructing such a DSP with LSI, the original development work relating to the basic processor and its software must be constructed anew by adding new functions, so that an evaluation chip needs to inevitably be developed anew, for testing purposes
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