Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process

DETAILED DESCRIPTION The present invention relates generally to silicon on insulator (SOI) wafers and more specifically to a new method and resulting structure for producing SOI wafers.
Prior art processings for producing silicon on insulator wafers have generally not had the desired thickness control.
A typical example of manufacturing is illustrated in FIGS.
1A through ID.
A thin layer of silicon-germanium 12 is formed on a silicon wafer 10.
A silicon layer 14 is epitaxially grown on the silicon-germanium layer 12 having an interface at surface 16 and an exposed surface 17.
A silicon handle 20 with an insulative layer, for example silicon dioxide 18, is bonded to surface 17 of the epitaxial layer 14.
The original wafer 10 is then removed using the silicon-germanium layer 12 as a removal or etch stop.
Subsequently, the silicon-germanium layer 12 is removed by etching which also removes a portion of the epitaxial layer 14.
Thus the ultimate thickness of the layer 14 is a function of the etching control versus the epitaxial growth control.
The resulting surface modified 16' in which the devices are formed has defects resulting from the etching and removal processing steps This is not a fresh virgin surface.
Another common problem with silicon on insulator substrates is that a back channel may be formed along surface 17 since substrate 20 can act as a gate with the insulative layer 18 acting as the gate insulator.
As illustrated in FIG.
2 a parasitic back channel can form at the surface 17 which electrically connects the N+ diffusions 22.
This is a serious problem in SOI CMOS devices when the thickness of the epitaxial layer 14 is such that the drain and source diffusions of the NMOS devices `bottom out` onto the buried oxide layer 18.
Under conditions where ionizing radiation is present (such as in outer space, for instance) holes trapped in the buried oxide layer 18 can cause a parasitic channel to form at the surface 17 of the NMOS devices leading to circuit failure.
Thus it is an object of the present invention to provide a method for fabricating silicon on insulator wafers with improved thickness control