Plasma pretreatment with BCl.sub.3 to remove passivation formed by fluorine-etch

DETAILED DESCRIPTION Referring now to FIGS.
1 thru 4, there are shown cross-sectional views of portions of a partially completed exemplary VLSI silicon-gate MOS device 10 illustrating various stages of an etching operation during its manufacture.
The same reference numbers are used throughout FIGS.
1 through 4 to denote like regions and portions of the device.
The device is a 64 kilobit dynamic RAM which uses two levels of polysilicon respectively designated POLY I and POLY II.
The etching operation being illustrated is for the patterning of the POLY II level.
As shown in FIG.
1, the POLY I level II, which is heavily doped and 4000 Angstroms thick, has been previously patterned to form one plate of a storage capacitor of a dynamic memory cell, the other plate of the capacitor being provided by a p-type region 13 of a single crystalline silicon body separated from layer 11 by a 300 Angstroms thick silicon dioxide layer 12.
Etching of the POLY I level was masked by a 2700 Angstroms thick intermediate silicon dioxide layer 14.
A silicon dioxide layer 15 was thermally grown on the sidewalls of the POLY I layer after etching.
Owing to undercutting of the POLY I level during etching, an oxide step 16 adjacent to the sidewall of the POLY I layer was formed with a re-entrant shape.
Prior to patterning, the POLY II layer 17, which is undoped and 5000 Angstroms thick, covers the intermediate oxide layer 14 and a 500 Angstroms thick silicon dioxide layer 18.
In another portion of the device, the POLY II layer contacts a heavily doped n-type region 19 of the silicon body through an aperture 20 in oxide layer 18.
A strip-like silicon dioxide layer 21, 2500 Angstroms thick and 2 .
mu.
m wide, is formed to serve as a mask for the etching of the POLY II layer to form a bit-line of the memory cell array.
In another portion of the device not depicted, the POLY II layer is patterned in the same etching operation to form gate electrodes of transistors and circuit interconnections.
Since the dimensions of the bit-lines and the gate electrodes are critical to the performance of the device, it is advantageous to pattern the POLY II layer using an etch which provides a high degree of anisotropy to obtain accurate feature size control