Tunable directional optical waveguide couplers

DETAILED DESCRIPTION With reference to FIG.
1, the substrate for the PLC is shown at 11.
The substrate may be glass or other suitable rigid support.
The preferred substrate material is silicon which is used in so-called optical bench technology for high quality optical integrated circuits.
The technology used in processing state of the art PLCs follows, in some respects, silicon IC wafer fabrication.
With reference again to FIG.
1, two waveguides are shown at 12 and 13, with a coupling section where the waveguides run parallel and closely spaced to one another.
The length of the coupling section is designated L.
The coupling region, i.
e.
the space between the waveguides along the coupling section, is designated 14 in the figures.
The basic operation of a directional coupler is well known.
It splits lightwaves coherently in a manner similar to a beam splitter in bulk optics.
The input lightwave to waveguide 12 is P.
sub.
i and the output lightwave from waveguide 13 is P.
sub.
o.
When the waveguides are closely spaced, as in FIG.
1, the evanescent tail of the lightwave in waveguide 12 extends into waveguide 13 and induces an electric polarization.
The polarization generates a lightwave in waveguide 13, which couples back to waveguide 12.
In the example given, the two waveguides are single mode and are parallel and identical in structure in the coupling region.
Both waveguides bend away from each other at the ends as shown, and gradually decouple.
The input lightwave P.
sub.
i and the output lightwave P.
sub.
o are related by: P.
sub.
i =kP.
sub.
o where k is the coupling ratio.
The coupling ratio is strongly affected by the coupling region, and in particular by the core-to-cladding refractive index difference which is temperature dependent.
This dependency can be utilized to adjust the coupling ratio after the fabrication of the waveguides has been completed.
The basic structure for accommodating this thermo-optic control is shown in FIG.
2 which is a section through 2--2 of FIG.
1.
In this view the silicon substrate 21, the lower cladding layer 22 and the upper cladding layer 23 can be seen