ATM address translation method and apparatus

DETAILED DESCRIPTION The present invention provides a unique method and apparatus for performing an address translation in an ATM network element, such as a switch, resulting in minimized circuit complexity and resultant cost savings.
Specifically, the present invention is directed towards address translation in preparation for addressing a virtual circuit table (VCT).
The present invention includes the identification of a range of significant bits for VPI and VCI which will be supported.
VPI and VCI values from received cells are truncated according to the identified range of values.
The truncated values are then zero-extended as required to equal the length of the total number of connections supported.
One of the two zero-extended values, VPI or VCI, is then reversed and logically OR'd with the remaining zero-extended, non-reversed value to form a local address suitable for addressing the virtual circuit table.
Each of the truncated, zero-extended values of VPI and VCI are also individually employed as masks for out-of-range checking.
The non-truncated version of VPI or VCI, as received, is exclusive-OR'd (XOR'd) with the respective truncated, zero-extended version of either VPI or VCI.
The resulting bits of the XOR are OR'd together.
If any bits of VPI or VCI, as received, beyond the range supported by this network element are set, one or more bits of the XOR result will have the value of "one".
Thus, the result of the respective OR operation will also be a "one".
This then indicates that the value of VPI or VCI as received is out of range.
Since the least significant bits of each field (VPI or VCI) are at a fixed location within the local address, implementation complexity is reduced compared to prior art concatenation approaches.
Specifically, many of the functions involved in the foregoing manipulations of VPI and VCI are implemented via hardwiring, rather than requiring use of expensive gates in a Field Programmable Gate Array (FPGA).