Apparatus for dispatching data of the highest priority process having the highest priority channel to a processor

DETAILED DESCRIPTION In accordance with the above and other objects of the invention, a priority interrupt and dispatcher mechanism is provided to continuously monitor internal or external interrupt requests from processes desiring control of the processor and determine whether or not the requesting processes have a higher level of priority than the executing process and award control of the processor to the highest priority process on the highest priority port.
Interrupts in the processor are assigned to one of eight priority levels (although any number of priority levels may be utilized) with level zero being the highest priority level and level seven being the lowest.
In order to minimize the time required to answer an interrupt request, the processor provides a complete set of registers for each of the eight levels.
When an interrupt causes the initiation of a new process, the current process is left intact in the registers assigned to the current level.
Control may be returned to the interrupted process simply by reactivating that process level.
The need to safestore and restore interrupt processes is eliminated, along with the accompanying overhead.
There are typically 16 registers 130-133 for each level in the 128-word processor scratchpad registers of each processor 103-106.
Since level zero may never be interrupted, the process state register for level zero is never transferred to the scratchpad memory; however, register 0 of level 0 is utilized to hold a control block base which contains the base address in memory of the exception control block or the interrupt control block which in turn is utilized to provide the address of an interrupting or interrupted process.
(See Steering Code Generating Apparatus for Use in an Input/Output Processing System of G.
Wesley Patterson, et al.
, U.
S.
Ser.
No.
562,362, filed on an even date with the instant application and assigned to the same assignee as the instant application).
The interrupt and dispatcher mechanism invention constantly monitors both the current process level of the processor and all requests for interrupt from any module attached to any port A-L or LM