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Associating buffers in a bus bridge with corresponding peripheral devices to facilitate transaction merging
| Details |
Inventors: Chen, Wen-Tzer Thomas; Kelley, Richard A.; Neal, Danny Marvin; Thurber, Steven Mark;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Beausoleil; Robert
Assistant Examiner: Phan; Raymond N.
Attorney, Agent or Firm: Lally; Joseph P., Van Leeuwen; Leslie A.
A bus bridge including a buffer pool and steering logic where the buffer pool is organized as a plurality of buffers sets including at least first and second buffer sets and the steering logic is adapted to store transactions originating with a first peripheral device in the first buffer set and transactions originating with a second peripheral device in the second buffer set. Transactions may arrive via a secondary bus, such as a PCI bus, coupled to the bus bridge. The bridge further allows relaxed transaction ordering rules compared to conventional PCI transaction ordering rules by identifying transactions by grant signals and thus allows steering of transactions from the first and second devices to first and second buffer sets respectively. The bridge is suitably adapted for combining or merging two or more transactions within each buffer set. Each buffer set preferably includes one or more buffers for temporarily storing transactions arriving from the secondary bus and bound for a primary bus. The primary bus may comprise a host bus connected to one or more processors or an additional PCI bus or other peripheral bus. The invention further contemplates a computer system including at least one processor, a bridge coupled to the processor via a host bus, and a plurality of peripheral devices including first and second peripheral devices coupled to the bridge via a secondary bus. In one embodiment, the bridge is configured to receive first and second request signals from the first and second peripheral devices respectively. The bridge preferably further includes arbitration logic for arbitrating mastership of the secondary bus in response to the request signals to produce first and second grant signals. The steering logic is suitably configured to utilize the first and second grant signals to determine the source of a subsequent transaction. |
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DETAILED DESCRIPTION The problems identified above are in large part addressed by a system and bus bridge design in which the bridges buffer pool is organized into multiple buffer sets and configured to associate each buffer set with a corresponding peripheral device.
With this organization, the source of buffered transactions can be maintained without requiring tag bits or other information not in compliance with existing bus specifications.
The source information can be utilized beneficially to improve the performance and reduce overhead associated with a variety of tasks and routines.
Broadly speaking, a first application of the present invention contemplates a bus bridge including a buffer pool and steering logic.
The buffer pool is organized as a plurality of buffer sets including at least a first and second buffer set.
The steering logic is adapted to store transactions originating from a first peripheral device to the first buffer set and transactions originating from a second peripheral device to the second buffer set thereby preserving origin information associated with each buffered transaction.
In one embodiment, the transactions arrive via a secondary bus, such as a PCI bus, coupled to the bus bridge.
The bridge is suitably adapted for combining two or more transactions within each buffer set to produce a single transaction.
Each buffer set preferably includes one or more buffers for temporarily storing transactions arriving from the secondary bus and bound for a primary bus that is coupled to the bus bridge through bus interface logic.
The primary bus may comprise a host bus connected to one or more processors.
Alternatively, the primary bus may comprise an additional PCI bus or other peripheral bus.
The first application of the present invention further contemplates a computer system including at least one processor, a bridge coupled to the processor via a host bus, and a plurality of peripheral devices including first and second peripheral devices coupled to the bridge via a secondary bus
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Processing Data 
