CMOS Logic circuit

DETAILED DESCRIPTION It is, therefore, an object of the present invention to provide a CMOS logic circuit which can perform a high-speed operation without an increase in the signal delay time even if the number of input signals is increased, which can decrease a pattern area and power consumption, and which does not require that consideration be given to a priority order of input signals.
According to an aspect of the present invention, there is provided a CMOS logic circuit comprising: a voltage source; a plurality of input terminals of the CMOS logic circuit; MOSFETs of a first conductivity type, each of which has one terminal connected to a corresponding one of the input terminals of the CMOS logic circuit, the other terminal connected to a common node, and a gate; delay elements connected between the input terminals of the CMOS logic circuit and the gates of the MOSFETs of the first conductivity type, respectively; an output inverter having an input terminal connected to the common node and having an output terminal; an output terminal of the CMOS logic circuit which is connected to the output terminal of the output inverter; and a MOSFET of a second conductivity type which has one terminal connected to the input terminal of the output inverter, the other terminal connected to the voltage source, and a gate connected to the output terminal of the output inverter.