Circuit for synchronizing an oscillator to a pulse train

DETAILED DESCRIPTION What is claimed is: 1.
An electric circuit comprising a voltage-controlled oscillator having an output; means for connecting to said oscillator output to provide clock pulses; and a phase comparator having a clock input, a further input for receiving a train of input pulses, and means for producing a control signal for said oscillator responsive to a phase relationship between said clock pulses and said train of input pulses, characterized in that said comparator comprises a single exclusive-OR gate for receiving delayed input pulses, having two inputs, a single D-type flipflop only, having an output connected to one of said exclusive-OR gate inputs, and a clock input to which said clock pulses are applied, and means for providing a pulse train to the other of said gate inputs, having a delay time of approximately half a clock period with respect to said train of input pulses; and said means for producing comprises a combinatory network having two network inputs, an output of said single exclusive-OR gate being connected to one of said network inputs, said combinatory network comprising means for forming a first and a second signal which have respectively opposite logic values when the clock pulses and input pulses are in phase, and which during a portion of each clock cycle have a same logical value when said clock pulses and input pulses are not in phase, the duration of said portion being a function of the magnitude of the difference in phase between said clock and input pulses, and the sense of the logical value being responsive to the sense of the phase difference.
2.
A circuit as claimed in claim 1, characterized in that said means for providing comprises a pulse delaying element having an output connected to said one of said exclusive-OR gate inputs, the output of said flipflop being connected to the other of said exclusive-OR gate inputs, said train of input pulses being applied both to said pulse delaying element and to the D input of the D-type flipflop.
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