Circuitry for the timing data output enable pulses

DETAILED DESCRIPTION It is, therefore, an object of the present invention to improve the apparatus for timing the generation of output enable signals.
It is another object of the present invention to provide apparatus for allowing a single output enable signal to control the operation of a plurality of computer chips.
It is yet another object of the present invention to provide circuitry which precisely determines the length of a dead cycle between output enable signals.
These and other objects of the present invention are realized in a circuit for providing data output enable signals to a device comprising means for generating an output enable signal in response to the simultaneous application of a clock signal and a second signal, and means for terminating the output enable signal in response to the termination of the second signal alone.
These and other objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.