Clock synchronous semiconductor memory device

DETAILED DESCRIPTION What is claimed is: 1.
A semiconductor memory device for taking in an external signal in synchronization with an external clock signal, comprising an input buffer responsive to an inactive level of said external clock signal for attaining a through state to pass therethrough said external signal, and responsive to an active level of said external clock signal for attaining a latch state to hold a signal in a logic level corresponding to the external signal applied at the time of a transition of said external signal to said active level, and internal circuitry coupled to said input buffer and responsive to the active level of the external clock for being activated to perform a preallotted operation on the signal received from said input buffer.
2.
A synchronous semiconductor memory device taking in an external signal including a control signal and an address signal in synchronization with an external clock signal, comprising, control means for taking in the control signal in synchronization with said external clock signal and generating an address hold instruction signal according to that taken in control signal in response to said external clock signal; hold means for holding and outputting an applied address signal in synchronization with said external clock signal; and latch means responsive to said address hold instruction signal for latching an address signal from said hold means and generating an internal address signal.
3.
A synchronous semiconductor memory device taking in an external signal including a control signal and an address signal in synchronization with an external clock signal, comprising: clock generation means for generating an internal clock signal in synchronization with said external clock signal; resetting means receiving the internal clock signal from said clock generation means for generating a control signal, said control signal attaining an active state after a prescribed time period from an activation of said internal clock signal; and a reset element responsive to said control signal for inactivating the internal clock signal from said clock generation means