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| Coin handling device |
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| Wide band automatic gain control with limiting amplifiers |
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| Television receiver having an automatic radiofrequency resonant circuit adjustment circuit |
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| Transfer device for use in retention type electrophotographic copying machine |
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| Switching network having improved turn-on capability |
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Correlation computing device for image signal
| Details |
Inventors: Uomori, Kenya; Ishii, Hirofumi; Morimura, Atsushi;
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP)
Primary Examiner: Clark; David L.
Assistant Examiner: Nguyen; Long T.
Attorney, Agent or Firm: Stevens, Davis, Miller & Mosher
A correlation computing device includes a higher-order bit elimination circuit which receives a digital input image signal and provides an output signal in which higher-order bits up to 50% have been eliminated as a maximum word length of a digital input image signal. A representative point preservation memory temporarily stores the output signal from the higher-order bit elimination circuit. A correlation determining circuit determines a correlation between a signal stored in the representative point preservation memory and the output signal from the higher-order bit elimination circuit. A minimum-value address decision circuit selects a minimum value of the correlation determined by the correlation determining circuit and determines a motion vector for the digital input image signal. |
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DETAILED DESCRIPTION With a view to solve the prior art problems pointed out above, it is an object of the present invention to provide an improved correlation computing device which can reduce the circuit scale without lowering the accuracy of motion vector detection.
The correlation computing device of the present invention which attains the above object comprises a high-order bit eliminating circuit eliminating high-order bits out of a digital input signal, a subtractor and an absolute value conversion circuit, thereby computing correlation between digital input signals of two successive image fields (or frames).
Practically, the proposed correlation computing device decreases word length by eliminating high-order bits out of digital input signal.
In conventional methods so far, decrease of word length has been done by eliminating low-order bits.
However, the accuracy of the calculation is lowered.
Therefore, in this invention, loss of accuracy is prevented by employing a high-order bit elimination, in which an overflow of data does not occur so far as the required word length of the output of the absolute value conversion circuit does not exceed the decreased word length with the high-order bit elimination (as explained in the embodiments described hereinbelow).
Since the regions for computing the correlation between image frames are relatively small, and since there exist strong correlation between spatially adjacent image data, rarely having steep changes because of the statistical characteristics of image data signals, the outputs of the absolute value conversion circuit are generally kept small, and therefore, the probability of occurrence of data overflow is kept small.
Further, the correlation is not calculated with a single operation, but a statistical calculation (actually, it is a cumulative addition) of a plurality of intermediate results of operations is included, so that influence of the rarely occurring overflows upon the accuracy of calculated correlation values can be substantially negligible
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Processing Data 
