|
|
Method and apparatus for synchronizing data received in an accelerated graphics port of a graphics memory system
The present invention provides a method and apparatus for receiving and synchronizing data transmitted to a host interface unit of a graphics memory system on the rising ...
|
|
|
Transmission system with improved synchronization
The object of the present invention is to provide a transmission system according to the preamble in which it is possible to transfer accurate timing information in said ...
|
|
|
Interface circuit device for performing data sampling at optimum strobe timing by using stored data window information to determine the strobe timing
An object of the invention is to provide an interface circuit, which can accurately transfer data to any one of semiconductor devices in a system. Another object of the ...
|
|
|
Managing connection requests in a dialup computer network
It is thus a primary goal of the present invention to manage service requests in a dialup computer network. It is a more particular object of the invention to redirect ...
|
|
|
Access-method-independent exchange 3
The present invention provides a virtual network, sitting "above" the physical connectivity and thereby providing the administrative controls necessary to link various ...
|
|
|
Fixed interconnection network method and apparatus for a modular mixed-resolution, N-dimensional configuration control mechanism
According to the present invention, as embodied and broadly described herein, a configuration control mechanism for dynamically and logically renaming elements of a ...
|
|
|
Semiconductor processing systems
OF THE PREFERRED EMBODIMENTS This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws "to promote the ...
|
|
|
Read crossbar elimination in a VLIW processor
OF THE PREFERRED EMBODIMENTS FIG. 2 shows a VLIW processor according to the invention. The processor has an IIR 201 with m issue slots, S.sub.0, S.sub.1, . . . , S.sub....
|
|
|
Method and system for maintaining strong ordering in a coherent memory system
The above and other needs are met by a method and system of strong ordering that uses timestamp signals to indicate the order in which transactions are sent to each ...
|
|
|
System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom
The problems outlined above are in large part solved by an improved bus interface unit hereof. The present bus interface unit can dispatch memory-destined request cycles ...
|
Processing Data 
