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| Access-method-independent exchange 3 |
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| Semiconductor processing systems |
| OF THE PREFERRED EMBODIMENTS This disclosure of the invention is submitted in furtherance of the ... |
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| Read crossbar elimination in a VLIW processor |
| OF THE PREFERRED EMBODIMENTS FIG. 2 shows a VLIW processor according to the invention. The ... |
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| Method and system for maintaining strong ordering in a coherent memory system |
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| Network data flow control technique |
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Data transaction typing for improved caching and prefetching characteristics
| Details |
Inventors: Christie, David S.; McMinn, Brian D.; Meier, Stephan G.; Pickett, James K.;
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Primary Examiner: Ellis; Kevin L.
Assistant Examiner:
Attorney, Agent or Firm: Conley, Rose & Tayon, PC, Merkel; Lawrence J.
A microprocessor assigns a data transaction type to each instruction. The data transaction type is based upon the encoding of the instruction, and indicates an access mode for memory operations corresponding to the instruction. The access mode may, for example, specify caching and prefetching characteristics for the memory operation. The access mode for each data transaction type is selected to enhance the speed of access by the microprocessor to the data, or to enhance the overall cache and prefetching efficiency of the microprocessor by inhibiting caching and/or prefetching for those memory operations. Instead of relying on data memory access patterns and overall program behavior to determine caching and prefetching operations, these operations are determined on an instruction-by-instruction basis. Additionally, the data transaction types assigned to different instruction encodings may be revealed to program developers. Program developers may use the instruction encodings (and instruction encodings which are assigned to a nil data transaction type causing a default access mode) to optimize use of processor resources during program execution. |
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DETAILED DESCRIPTION The problems outlined above are in large part solved by a microprocessor in accordance with the present invention.
The microprocessor assigns a data transaction type to each instruction.
The data transaction type is based upon the encoding of the instruction, and indicates an access mode for memory operations corresponding to the instruction.
The access mode may, for example, specify caching and prefetching characteristics for the memory operation.
The access mode for each data transaction type is selected to enhance the speed of access by the microprocessor to the data, or to enhance the overall cache and prefetching efficiency of the microprocessor by inhibiting caching and/or prefetching for those memory operations.
Advantageously, the instruction encoding is used to determine caching and prefetching characteristics.
Instead of relying on data memory access patterns and overall program behavior to determine caching and prefetching operations, these operations are determined on an instruction-by-instruction basis.
Cache and prefetch efficiency may be increased, and hence overall microprocessor performance may be increased as well.
Additionally, the data transaction types assigned to different instruction encodings may be revealed to program developers and compiler developers.
Program developers may use the instruction encodings (and instruction encodings which are assigned to a nil data transaction type causing a default access mode) to optimize use of processor resources during program execution.
Similarly, compilers may be designed to select appropriate instruction encodings based upon the type of data being manipulated by each instruction.
Even more performance may be gained through the judicious choice of instruction encodings.
Broadly speaking, the present invention contemplates a microprocessor comprising a decode unit and a load/store unit.
The decode unit is coupled to receive an instruction and configured to determine a data transaction type corresponding to the instruction
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Processing Data 
