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Home Processing Data Direct-memory-access-controller-for-handling-cyclic-execution-of-data-transfer-in-accordance-with-stored-transfer-control-information

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 Direct memory access controller for handling cyclic execution of data transfer in accordance with stored transfer control information

Details
Inventors: Taniai, Takayoshi; Tanaka, Yasuhiro; Saitoh, Tadashi;
Assignee: Fujitsu Limited (Kawasaki, JP)
Primary Examiner: Gossage; Glenn
Assistant Examiner: Kim; Matthew M.
Attorney, Agent or Firm: Armstrong, Westerman, Hattori, McLeland & Naughton

A direct memory access controller coupled to a system bus of a system for controlling data transfers through a channel includes the following. A request handler receives a transfer request generated by a device connected to the system bus. A transfer control information register stores transfer control information used for obtaining transfer control information necessary for executing the data transfer by a next transfer request supplied from the request handler. A temporary register stores the transfer control information necessary for processing the next transfer request. A transfer control information setting circuit generates the transfer control information necessary for processing the next transfer request on the basis of the transfer control information registered in the transfer control information register during the data transfer by the present transfer request and then renewing the transfer control information and-temporary registers with the generated transfer control information. A transfer execution circuit executes the actual data transfer through the system bus in accordance with the transfer control information registered in the temporary register, which is output to the system bus therefrom.

DETAILED DESCRIPTION It is therefore a general object of the present invention to provide a novel and useful direct memory access controller in which the above-mentioned disadvantages of the conventional art are eliminated.
A more specific object of the present invention is to provide a direct memory access controller in which transfer control information necessary for the next transfer request is generated beforehand, and is immediately output after the request of the above next DMA transfer request occurs.
Thereby, it becomes possible to extremely reduce the response time and increases the DMA processing speed.
A direct memory access controller for controlling data transfer through a system bus comprises the following: request handling means for receiving a transfer request generated by a device connected to said system bus; first register means for storing first transfer control information used for obtaining second transfer control information necessary for executing the data transfer by a next transfer request supplied from said request handling means; second register means for storing said second transfer control information; transfer control information setting means for generating said second transfer control information necessary for executing the data transfer by the next transfer request on the basis of the first transfer control information registered in said first register means during the data transfer by a present transfer request prior to the next transfer request and for writing said second transfer control information into said second register means during the data transfer by the present transfer request; and transfer execution means for reading out said second information from said second register means when the data transfer by the next transfer request is executed and for executing the data transfer through said system bus in accordance with the second transfer control information.
Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings



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