Distributed-memory multiprocessor computer system with directory-based cache coherency with ambiguous mappings of cached data to main-memory locations

DETAILED DESCRIPTION In the course of the present invention, it was determined that for certain types of user programs, e.
g.
, large databases, recalls following main-memory accesses are frequent enough to significantly impair performance of distributed-memory multiprocessor systems with four or more cells.
Furthermore, the impairment scales more than linearly with the number of cells.
Thus, the larger the system, the greater the need to address this performance impairment.
One solution considered is to store the main directory in faster memory than main memory.
However, the cost of providing SRAMs large enough to store an entire coherency directory appears commercially infeasible.
Accordingly, the present invention provides fast coherency directories containing some, but not all, of the information in the main coherency directories.
Each fast directory is accessed concurrently with its respective main directory.
Because information can be retrieved from the fast directory sooner than it can be retrieved from the main directory, some recalls can be initiated before main-memory access is completed.
To the extent that these recalls are correctly issued, the frequency with which recalls are issued following a main-memory access is reduced.
Thus, overall system performance is enhanced.
Required recalls not indicated by the fast directory can be issued once the main-directory data is retrieved from main memory.
To take cost-effective advantage of relatively fast-but-expensive memory devices (e.
g.
, SRAM versus DRAM), the fast directory should be much smaller than the main directory.
The fast directory can be shallower, i.
e.
, represent fewer lines than the main directory, or it can be narrower than the main directory, i.
e.
, contain fewer bits per line represented, or, preferably, both.
In the case the fast directory is shallower than the main directory, it is preferably operated as a cache so that the lines represented are varied according to usage.
While caches typically require tags to be stored with user data, the present invention provides for caches without tags or with incomplete tags