Dynamic mechanism to upgrade o state memory-consistent cache lines

DETAILED DESCRIPTION In view of the above and other shortcomings in the art recognized by the present invention, the present invention introduces an O cache consistency state that permits unrequested memory-consistent and possibly non-coherent data to be stored in a cache, thereby reducing a processor's access latency to memory-consistent data.
A multiprocessor data processing system in accordance with the present invention includes an interconnect, a plurality of processing units coupled to the interconnect, and at least one system memory and a plurality of caches coupled to the plurality of processing units.
A cache suitable for use in such a data processing system includes data storage containing a data granule, a state field associated with the data granule, and a cache controller.
The state field has a plurality of possible states including an O state that indicates that the data granule is consistent with corresponding data in the memory and has unknown coherency with respect to other peer caches among the plurality of caches.
To update the state of the data granule from this first state, the cache controller issues on the interconnect a transaction specifying an address associated with the data granule.
In response to receipt of a combined response of the plurality of caches, the cache controller updates the state field to a second state among the plurality of possible states.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.