Dynamic memory with high speed nibble mode

DETAILED DESCRIPTION In accordance with one embodiment of the invention, a semiconductor dynamic memory device has an array of one-transistor cells, with row and column decode to produce a 4-bit wide input or output.
Single-bit data-in and data-out terminals for the device may be coupled to the 4-bit array input/output in a sequential mode.
The row and column addresses are latched when RAS and CAS drop, and this includes the address of the starting bit within the 4-bit sequence.
The other three bits follow as CAS is cycled.
This starting address is used to set a bit in a 4-bit ring counter, which is then used to cycle through the sequence.
Although described herein using a four-bit nibble as an example, the circuitry and features of the invention can be used for a serial byte mode (8-bits), or any other number as may be appropriate.