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Failure analysis device for memory devices
| Details |
Inventors: Tanabe, Keiji;
Assignee: Ando Electric Co., Ltd. (Tokyo, JP)
Primary Examiner: Beausoliel, Jr.; Robert W.
Assistant Examiner: Fisch; Alan M.
Attorney, Agent or Firm: Finnegan, Henderson, Farabow, Garrett & Dunner
A physical image converting circuit is used in a memory tester for or an integrated circuit tester analyzing the failure of storage devices to be measured, in which data are read as logical images from each of the corresponding storage regions to each input/output bit and are stored in each of the corresponding storage regions to each input/output bit of a failure analysis memory used for failure analysis. The physical image converting circuit converts the logical image of the readout data from the failure analysis memory into physical images so that the readout data corresponds to a physical position on a wafer chip of the failure analysis memory. The physical image converting circuit includes a counter, an address converting circuit, a failure analysis memory, and a selector. The counter generates increment addresses corresponding to at least a storage capacity of failure analysis memory. The address converting circuit generates data X and Y for specifying X and Y addresses and data P for specifying the input/output bit of the failure analysis memory based on the increment addresses. The selector selects the specified data by the data P among the readout data from the corresponding storage region of the failure analysis memory to the specified X and Y addresses by the data X and Y. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, a preferred embodiment of the present invention will be explained with reference to FIG.
1.
FIG.
1 shows a block diagram of the structure of a physical image converting circuit based on the preferred embodiment of the present invention in the case where the failure analysis memory 7 has the physical alignment of memory cells shown in FIG.
7.
In FIG.
1, components which correspond to components in the conventional physical image converting circuit shown in FIG.
6 are given the same identifying numerals.
In FIG.
1, an address converting circuit 11 includes selectors 2 and 6, a register 3, and exclusive OR gates (hereafter referred to as EOR gates) 4 and 5.
In FIG.
1, the counted value of the counter 1 is supplied to the selector 2 and a first input terminal of the EOR gate 5 as the address represented by the bit data A0 through A4.
The selector 2 selects arbitrary bit data among the bit data A0 through A4 supplied from the counter 1 and supplies output bit data SO through S4 including the selected bit data to a first input terminal of the EOR gate 4.
The register 3 supplies the prestored bit data R0 through R4 to a second input terminal of the EOR gate 4.
The EOR gate 4 carries out exclusive OR operation for the bit data S0 through S4 and the bit data R0 through R4 and supplies the resultant bit data N0 through N4 to a second input terminal of the EOR gate 5.
The EOR gate 5 carries out exclusive OR operation for the bit data A0 through A4 and the bit data NO through N4 and supplies the resultant bit data D0 through D4 to the selector 6.
In the case where the failure analysis memory 7 has the physical alignment of the memory cells shown in FIG.
7, the relationship between the 5-bit data A0 through A4 consisting of the counted value of the counter 1, the bit data X0 and X1 consisting of the X address, the bit data Y0 consisting of the Y address, and the bit data (P0, P1), are represented by formulas (1) through (5).
X0=A0.
sym.
A2 (1) X1=A1
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Processing Data 
