Configuration memory for programmable logic device |
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Serial access semiconductor memory having a reduced number of data registers |
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Method and apparatus for the synchronization of a cascaded multi-channel data transmission |
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Perforated debris catcher for a nuclear fuel assembly |
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Dynamic memory with high speed nibble mode |
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Local bus interface |
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Sampling signal analyzer |
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Synchronous read channel employing an expected sample value generator for acquiring a preamble |
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Fixed interconnection network method and apparatus for a modular mixed-resolution, N-dimensional configuration control mechanism
| Details |
Inventors: Estes, Mark D.;
Assignee:
Primary Examiner: Shah; Alpesh M.
Assistant Examiner:
Attorney, Agent or Firm: David Newman & Associates, P.C.
A modular, polymorphic network interconnecting a plurality of electronically reconfigurable devices via a modular, polymorphic interconnect, to permit a fixed, physical configuration of operating hardware devices to take on a plurality of logically addressable configurations. The modular, polymorphic interconnect further permits allocation and deallocation of selected electronically reconfigurable devices for a particular logically addressable configuration. The modular, polymorphic interconnect additionally permits the logical topology of selected electronically reconfigurable devices to be configured as at least one mixed-radix, N-dimensional network. The logical topology of mixed-radix, N-dimensional networks can be dynamically changed under control for a new configuration of logical addresses for selected electronically reconfigurable devices. The modular, polymorphic interconnect also permits one or more electronically reconfigurable devices to be selected from at least one logically related set of electronically reconfigurable devices, making the resulting network system particularly well suited for a variety of purposes related to resource management. |
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DETAILED DESCRIPTION According to the present invention, as embodied and broadly described herein, a configuration control mechanism for dynamically and logically renaming elements of a mixed-radix, N-dimensional object space is provided. A primary object of the invention is to provide a network architecture that dynamic reconfigures itself based on the state of the machine as well as a predetermined control sequence. Whereas prior art configuration control mechanisms typically load an externally precomputed control sequence from memory, the present invention dynamically generates a logical configuration in accordance with the method disclosed in a U. S. patent application by Estes and Walker entitled MIXED-RESOLUTION, N-DIMENSIONAL OBJECT SPACE METHOD AND APPARATUS, having Ser. No. 07/642,508 and filing date of Jan. 16, 1991, now U. S. Pat. No. 5,301,284, which is incorporated herein by reference. An object frame is specified as input to the configuration control mechanism of the present invention, which responds logically by configuring the interconnections of the elements of a modular object space. The logical polarity of the inputs is manipulated by the configuration control mechanism to reconfigure the logical meaning of a common set of interconnections in response to object frame specifications. The configuration control mechanism comprises at least one module having a four-by-four array of elements, a first input circuit, a second input circuit, a third input circuit, and a fourth input circuit. Each element may be a sensor, port, memory, pixel, processor, or any other device which may be addressed as a named element of a mixed-radix, N-dimensional object space. The configuration control mechanism of the present invention allows one or a plurality of modules to be selected from a set of such modules. Accordingly, multiple levels of control can dynamically configure a plurality of modules, thereby implementing an important form of context transition control. Additional objects and advantages of the invention are set forth in part in the description which follows, and in part are obvious from the description, or may be learned by practice of the invention
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