JTAG instruction error detection

DETAILED DESCRIPTION The noted need for error detection is met in accordance with the present invention wherein each JTAG component in a boundary scan path is arranged to detect errors in instructions shifted into the component.
In response to detected errors, the components connect a single bit bypass register into the scan path rather than the expected register.
Since JTAG control circuitry must know the length of the scan path which should be connected as the result of issued instructions so that it can shift in the appropriate signals required to perform the instructions, the shifting of the assembled signals into the scan path is used to determine whether an instruction error was received by the component.
In accordance with the preferred embodiment of the present invention, the data scanned into a component for performance of previously scanned instructions is prefixed by a header which is then monitored by the JTAG control circuitry to detect any instruction errors.
The header is preferably constructed to be as long as the longest register in the scan path and to have all 0s except for a number of 1s in its least significant bit positions which are equal to one less than the shortest register in the scan path or one if the shortest register in the scan path is equal to one.
The combined data and header are padded by bits preceding the header to be equal to a multiple of a data register contained within the JTAG control circuitry, commonly eight bits such that the combined data and header are often a multiple of eight.
It should be apparent that if any register expected to be connected into the scan path is replaced by a one bit bypass register that ones in the least significant bit positions of the header will be shifted out of the data register as will the padding bits prior to the time that the header or first byte of the header should have been in the data register of the JTAG control circuitry.
Accordingly, for single errors, the least significant bit of the data register of the JTAG control circuitry is examined when the data register should contain the first byte of the header