 Alarm server systems, apparatus, and processes |
| The present inventions will be described by referring to apparatus and methods showing various ... |
|
| Synchronous clock regenerator for binary serial data signals |
| In accordance with the present invention, the incoming raw clock signal with arbitrary phase is fed ... |
|
| Data transfer apparatus with automatic transmission rate adjustment |
| It is an object of the present invention to provide a data transfer apparatus capable of minimizing ... |
|
| Data acquisition method and protocol controller circuit |
| Briefly, the present invention is directed to a data acquisition circuit for acquiring transfer ... |
|
| Transmission system with improved synchronization |
| The object of the present invention is to provide a transmission system according to the preamble ... |
|
| Managing connection requests in a dialup computer network |
| It is thus a primary goal of the present invention to manage service requests in a dialup computer ... |
|
| Access-method-independent exchange 3 |
| The present invention provides a virtual network, sitting "above" the physical connectivity and ... |
|
|
Mechanism for PCI I/O-initiated configuration cycles
| Details |
Inventors: Creta, Kenneth C.; Moran, Doug; Shanmugasundaram, Vasudevan;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Auve; Glenn A.
Assistant Examiner: Patel; Nimesh
Attorney, Agent or Firm: Marger Johnson & McCollom, P.C.
Methods and apparatus for inbound PCI configuration cycles are disclosed. By definition, PCI bridges block upstream progress of configuration cycles initiated by a PCI bus master on their secondary buses. In the described embodiments, a PCI bus master can execute a configuration cycle despite this limitation, by converting the configuration cycle command to Memory Read and Write commands that a PCI bridge will forward upstream. The PCI bus master writes the address of a target configuration register to a first predefined address, and pushes or pulls data from that target register by subsequently initiating a memory access to a second predefined address. A platform chipset is designed to recognize Memory Read and Write accesses to the predefined addresses as relating to an inbound configuration cycle. When a memory access to the second address is received, the chipset uses the information stored at the first address to form and execute a configuration cycle on behalf of the downstream PCI bus master. |
|
DETAILED DESCRIPTION OF THE EMBODIMENTS The PCI local bus was intended to allow downstream configuration register access, i.
e.
, from host processor 30 and PCI controller 48 of FIG.
2.
Upstream configuration register access capability is, on the other hand, virtually non-existent for PCI-compliant devices.
According to the PCI-to-PCI Bridge Architecture Specification, a bridge is to ignore the following appearing at its secondary interface: all type 0 configuration transactions, whether read or write; all type 1 configuration read transactions; all type 1 configuration write transactions, unless used to trigger a "special cycle" upstream (special cycles do not access configuration registers).
Thus it is not possible for a bus agent to access configuration registers upstream of the PCI bus that the agent is attached to.
And it is not possible for that agent to access chipset configuration registers that exist in configuration address space, or configuration registers on a separate PCI bus that does not share the same PCI root controller.
The disclosed embodiments overcome the inability of PCI to service upstream, or "inbound" configuration cycles, preferably while remaining completely compliant with the relevant PCI specifications.
For instance, in a preferred method, a PCI agent signals the chipset to perform a configuration cycle for the agent; the signaling involves accessing predefined memory addresses, allocated to the chipset, with standard PCI memory read and write operations.
The chipset is specially configured to recognize accesses to those addresses as requests to perform a configuration on behalf of a device downstream of the chip set.
The chipset can always perform the requested cycle, since downstream configuration cycles are supported by PCI, and since it can access its own configuration registers.
If the requested configuration transaction is a register write, the chipset performs a configuration write command for the PCI agent.
If the requested configuration transaction is a register read, the chipset may instruct the PCI agent to retry its memory read later
|
|
Processing Data 
