Method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller

DETAILED DESCRIPTION A method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller is described herein.
The memory controller includes a data controller unit and a data path unit.
Signals are passed between the data controller unit and the data path unit, thereby providing an interface between the two units.
The data controller receives control signals from the bus and provides commands to the data path unit in response to these control signals.
The commands provided to the data path unit enable the data path unit to transfer data to and from the bus and memory device.