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Method and apparatus for performing N bit by 2*N-1 bit signed multiplications
| Details |
Inventors: Hoffman, Nathaniel;
Assignee: Intel Corportion (Santa Clara, CA)
Primary Examiner: Mai; Tan V.
Assistant Examiner:
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman LLP
A method and apparatus for performing N bit by 2*N (or 2*N-1) bit signed multiplication using two N bit multiply instructions. According to one aspect of the invention, a method for performing signed multiplication of A times B (where B has N bits and A has N*2 bits) is described. In this method, A.sub.high and A.sub.low respectively represent the most and least significant halves of A. According to this method, A.sub.low is logically shifted right by one bit to generate A.sub.low >>1. Then, A.sub.low >>1 is multiplied by B using signed multiplication to generate a first partial result. In addition, a second partial result is generated by performing signed multiplication of A.sub.high times B. One or both of the first and second partial results is shifted to align the first and second partial results for addition, and then the addition is performed to generate a final result representing A multiplied by B. |
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DETAILED DESCRIPTION A method and apparatus for performing N bit by 2*N (or 2*N-1) bit signed multiplication using two N bit multiply instructions is described.
According to one aspect of the invention, a method for performing signed multiplication of A times B (where B has N bits and A has N*2 bits) is described.
In this method, A.
sub.
high and A.
sub.
low respectively represent the most and least significant halves of A.
According to this method, A.
sub.
low is logically shifted right by one bit to generate A.
sub.
low >>1.
Then, A.
sub.
low >>1 is multiplied by B using signed multiplication to generate a first partial result.
In addition, a second partial result is generated by performing signed multiplication of A.
sub.
high times B.
One or both of the first and second partial results is shifted to align the first and second partial results for addition, and then the addition is performed to generate a final result representing A multiplied by B.
According to another aspect of the invention, a method and apparatus for performing N bit by 2*N (or 2*N-1) bit signed multiplication using a particular packed data instruction is described.
According to this method and apparatus, signed multiplication of at least a value A0 by a value B0 is performed.
The value A0 and B0 are respectively represented in N and 2*N bits.
In response to executing the particular instruction, the following is performed: 1) a first and second set of two data elements are read as part of a first set of two packed operands, wherein one data element in the first set of two data elements is zero, wherein one data element in the second set of two data elements represents B0, and wherein another data element in the second set of two data elements represents one of a most and least significant part of A0; 2) data elements in each of the first and second sets of two data elements are multiplied together to generate a pair of results; and 3) the pair of results are summed to generate a packed operand having a data element representing B0 multiplied by the one of the most and the least significant part of A0 found in the second set of two data elements
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Processing Data 
