Method and apparatus for retarting pipeline processing

DETAILED DESCRIPTION According to the invention, pipeline throughput is improved by a processing pipeline architecture in which processing interdependencies (such as the instruction latencies described above, resource conflicts, cache accesses, virtual address translations and sign extend operations) are presumed not to be present.
Interdependencies which actually occur appear as processing faults which then are serviced.
Faults classified as "interlocks" are serviced in hardware, while stalling the pipeline.
Faults classified as "exceptions" are serviced with software and handled conventionally.
At completion of interlock servicing, pipeline restart operations occur, during which portions of the pipeline are preloaded.
According to one aspect of the invention, the normal pipeline processing does not include stall states for avoiding potential interdependencies which may or may not be present.
Instruction latencies are assumed not to occur.
Similarly resource conflicts are assumed not to occur.
Accessing cache for fetching an instruction or data is done with the assumption that the instruction or data is present in cache.
Virtual address translations are assumed to be available in the translation buffer.
Sign extend operations are assumed not to occur.
If there is an instruction latency, resource conflict, invalid cache access, translation address miss or sign extend operation, a processing fault (i.
e.
, interlock) occurs.
According to another aspect of the invention, a pipeline restart process and apparatus is provided for preloading portions of the pipeline during an interlock fault recovery so that the pipeline is full when pipeline processing resumes.
State machines and control registers are defined for controlling the processor pipeline and the fault recovery procedures.
During each clock cycle, the pipeline is checked to evaluate all possible fault causing events.
If one or more interlock fault conditions are present, the faults are prioritized for servicing.
A processor state machine then switches the processor from a run state to a stall state as determined by the interlock to be serviced