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| High speed image processing computer |
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| Programmable logic device with two dimensional memory addressing |
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| Data transfer control device for controlling data transfer between shared memories of network clusters |
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| Exception reporting on function generation in an SIMD processor |
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| High performance digital electronic system architecture and memory circuit therefor |
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| Composite communication network |
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Method and apparatus for the synchronization of a cascaded multi-channel data transmission
| Details |
Inventors: Perloff, Ronald S.; Hamstra, James R.; Li, Gabriel M.; Yeung, Louise Y. Y.;
Assignee: National Semiconductor Corporation (Santa Clara, CA)
Primary Examiner: Olms; Douglas W.
Assistant Examiner: Chin; Stephen
Attorney, Agent or Firm: Limbach, Limbach & Sutton
A method and apparatus for synchronizing the cascaded, multi-channel transmission of a plurality of data characters is provided. Each sequence of data characters preceded by a start delimiter. Each transmission channel provides transmitted data frames to an associated elasticity buffer. As each channel detects a start delimiter, it asserts a begin-request signal that acknowledges detection of the start delimiter. When all channels have detected a start delimiter, a read-start signal is asserted to simultaneously advance the read pointer of each elasticity buffer. In this manner, each elasticity buffer initiates a sunchronized read for local use or retransmission of the multi-channel data. |
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DETAILED DESCRIPTION OF THE INVENTION An illustrative embodiment of the synchronization method and apparatus of the present invention will be described below in the context of a data transmission network in accordance with the Fiber Distributed Data Interface (FDDI) Physical Layer protocol which has been configured for multi-channel transmissions to provide higher bandwidth than an FDDI network.
It should be understood, however, that the concepts of the present invention are applicable to any multi-channel data transmission system.
The FDDI protocol is an American National Standards Institute (ANSI) data transmission standard which applies to a 100 Mbit per second token ring network that utilizes an optical fiber transmission medium.
The FDDI protocol is intended as a high performance interconnection among computers as well as among computers and their associated mass storage subsystems and other peripheral equipment.
In an FDDI network, information is transmitted between stations in data frames that are separated by interframe gaps of control characters.
Each frame consists of a sequence of 5-bit characters or "symbols", each symbol representing 4 data bits.
Information is typically transmitted in symbol pairs or "bytes".
Each frame is bounded by start and stop delimiters.
A start code comprising a unique start delimiter byte JK identifies the exact beginning of a frame.
Additional information regarding the FDDI protocol is presented by Floyd E.
Ross, "FDDI - an Overview", Digest of Papers, Computer Soc.
Intl.
Conf.
, Compcon '87, pp.
434-444, which is hereby incorporated by reference to provide additional background information for the present invention.
FIG.
1 shows a block diagram of an elasticity buffer 1 that may be utilized in practicing the present invention.
As shown in FIG.
1, elasticity buffer 1 is divided into a START section and a CONTINUATION section.
The START section includes two byte-wide registers: JK and SPEC.
The CONTINUATION section defines a cyclic buffer queue, that is, a series of sequentially accessed byte-wide storage registers A-D wherein access for a particular operation, i
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