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Method and apparatus to control cache memory in multiprocessor system utilizing a shared memory
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Inventors: Hamaguchi, Kazumasa; Shibayama, Shigeki;
Assignee: Canon Kabushiki Kaisha (Tokyo, JP)
Primary Examiner: Robertson; David L.
Assistant Examiner:
Attorney, Agent or Firm: Fitzpatrick, Cella, Harper & Scinto
In a multiprocessor system having a shared memory containing the state of the data for every entry in each cache memory possessed by each processor. The state of the data is set to a "shared state" when the data is shared with other cache memories, and is set to a "shared stale state" when the data in the "shared state" becomes stale by updating performed in another cache memory. Each processor monitors a transaction generated on a bus, derives a data portion from the bus when it is in the same address as the data in the "shared stale state" of its own cache memory, thereby updating the data in the address and making the state of the data a "shared state". |
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DETAILED DESCRIPTION It is an object of the present invention to provide a cache memory control method which is suitable for all kinds of software architectures.
It is another object of the present invention to provide a cache memory control method which produces little cache miss and does not require an extra processing time for unnecessary data updating.
It is still another object of the present invention to provide a cache memory control method wherein, when updating a data block in accordance with a cache miss produced in a cache memory, the same block in other cache memories can be updated.
According to one aspect, the present invention achieves these objectives using a method of controlling a cache memory for a processor in a multiprocessor system, which is equipped with a shared memory, the method comprising the steps of storing a state of data for every entry in each cache memory, monitoring by each processor the transactions generated on a system bus by another apparatus, checking whether or not an entry having a stale state in the same address as an address of the generated transaction is present in its own cache memory, deriving a data portion in the transaction as data of the entry if the entry is present, and validating the state of the data of the entry.
According to another aspect, the present invention achieves these objectives using a processor constituting a multiprocessor system by being connected to other processors via a system bus, the processor comprising cache memory means for storing the state of data for every entry together with the data, monitoring means for monitoring a transaction generated on the system bus by another apparatus, determining means for determining whether or not an entry having a state that is invalid in the same address as an address of the generated transaction is present in the cache memory means, and means for deriving a data portion in the transaction from the bus as data of the entry if the determining means has determined that the entry is present
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