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 Method and system for maintaining strong ordering in a coherent memory system

Details
Inventors: Chaney, Kenneth; Chastain, David M.; Patrick, David M.;
Assignee: Hewlett-Packard Co. (Palo Alto, CA)
Primary Examiner: Chan; Eddie P.
Assistant Examiner: Ellis; Kevin L.
Attorney, Agent or Firm:

A method and system of maintaining strong ordering in a multiprocessor computer system having a coherent memory. Memory transactions are send from one or more processors to a processor agent. The processor agent sends the transactions to a memory agent via a crossbar switch. The memory agent performs memory coherency operations and sends memory transactions back to the processor agents via the crossbar switch. The crossbar switch, however, may alter the order in which the memory transactions are forwarded to the processor agent. Therefore, the memory agent also sends a timestamp for each memory transaction directly to the processor agent via a dedicated link. An arbitrator within the processor agent receives the timestamps and the memory transactions. Using the timestamps, the arbitrator reorders the memory transactions and sends the transactions to the processors in the order in which the transactions were sent. In addition, the memory agent sends a parity signal with each timestamp. Specific combinations of parity signals and timestamps tell the arbitrator the type of transaction it will receive from the memory agent. Dependent upon the type of transaction, the arbitrator can change the order in which the transactions are sent to the processors.

DETAILED DESCRIPTION The above and other needs are met by a method and system of strong ordering that uses timestamp signals to indicate the order in which transactions are sent to each processor.
The timestamp signals travel via dedicated pathways having fixed transmission latencies.
Therefore, the processor always receives the timestamp signals in the order in which the signals were sent.
An arbitrator receives both the timestamp signals and the memory transactions.
The timestamp signals are buffered in the order in which they are received.
The memory transactions are received from a crossbar.
Since the crossbar may reorder the transactions, the arbitrator does not necessarily receive the transactions in the same order as they were sent.
By using timestamp signals, the arbitrator can rearrange the transactions into the proper order.
In addition, a parity bit accompanies each timestamp signal.
A specific sequence of timestamp and parity bits indicates that the corresponding transaction is a data return.
Since the transaction is a data return and not a purge operation, the arbitrator knows that it is safe to send other transactions out of sequence.
A technical advantage of the present invention is reduced latency on access to semaphores.
Since there is no need to wait for "purge done" responses, a data return can be sent at the same time as the purge transactions.
Therefore, there is no need to wait for the "purge done" responses before changing a semaphore.
Another technical advantage of the present invention is that logic is not needed to count the "purge done" responses before the semaphore is changed.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood.
Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention



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