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Home Processing Data Method-for-automated-deployment-of-a-software-program-onto-a-multi-processor-architecture

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 Method for automated deployment of a software program onto a multi-processor architecture

Details
Inventors: Hunt, Peter D.; Elliott, Jon K.; Tobias, Richard J.; Herring, Alan J.; Morgan, Craig R.; Hiller, John A.;
Assignee: Loral/Rohm Mil-Spec Corp. (San Jose, CA)
Primary Examiner: Shaw; Gareth D.
Assistant Examiner: Banankhah; Majid A.
Attorney, Agent or Firm: Perman & Green

A method is employed for pre-assignment and pre-scheduling of tasks that enables allocation across multiple physical processors arranged in a variety of architectures. The method comprises the steps of: constructing a DFG of tasks to be performed to provide a solution for a problem; determining cost values for each task and the overall problem, such cost values taking into account a target multiprocessor architecture and factors such as elapsed task execution times. The method pre-assigns the tasks to logical processors and assures that inter-dependent tasks are executable by logical processors that are within required communications delay criteria of each other. The assigning action attempts to arrive at a minimal cost value for all tasks comprising the problem. The pre-assigned tasks are then pre-scheduled based upon a performance criteria and are converted to machine code. The machine code is then deployed to physical processors in the target multi-processor architecture. The deploying action maps the logical processors' pre-assigned programs (comprising assigned tasks) onto physical processors, using data regarding the multi-processor architecture and the current utilization of the physical processors in the architecture, all while assuring that inter-dependent tasks are mapped so as to fulfill interprocessor communication delay criteria.

DETAILED DESCRIPTION OF THE INVENTION To enable the tasks comprising a complex problem to be deployed across processors in a multi-processor architecture, the invention employs a DFG of the problem solution to both pre-assign and pre-schedule the individual tasks that lead to an execution of the solution of the problem.
Each task is assigned to a "logical processor", a logical processor being a data structure that defines an eventual physical processor's functions and performance requirements.
In addition to assigned tasks, each logical processor is also assigned criteria which must be fulfilled when the task or tasks to be carried out by the logical processor are deployed onto a physical processor in a chosen multi-processor architecture.
The deployment of pre-assigned, pre-scheduled tasks is accomplished by using a map of available physical processors in the multi-processor architecture, as well as information describing the current utilization and interrelationships of the physical processors.
The above resume of the invention will be better understood by initially referring to FIG.
1.
In the known manner, a programmer employing a DFG software package constructs a flow graph 10 that illustrates various tasks that comprise a procedure for achieving a solution of a selected problem.
Such problems often involve arrays of data and lend themselves to solution on highly parallel, multi-processor architectures.
DFG 10 illustrates relationships between a plurality of tasks/primitives employed in the solution of an exemplary problem.
Data input to the DFG occurs via input nodes 12 and 14.
While each of primitives A-F can exhibit a wide range of complexities, each consists of a task that is predetermined and for which detailed performance data and code object file names already exist in the data base of a data processing system (e.
g.
a workstation) used to construct the DFG.
Once DFG 10 has been created, the programmer has produced a graph data base 15 that includes a node interconnect file 16 and an object screen positional file 18



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