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Home Processing Data Method-for-qualifying-biased-burn-in-integrated-circuits-on-a-wafer-level

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 Method for qualifying biased burn-in integrated circuits on a wafer level

Details
Inventors: Ports, Kenneth A.; St. Clair, Thomas R.;
Assignee: Harris Corporation (Melbourne, FL)
Primary Examiner: Peters; Jimmy C.
Assistant Examiner:
Attorney, Agent or Firm: Leitner, Palan, Martin & Bernstein

Integrated circuits in dice on a wafer are biased burn-in qualified by providing two sets of conductors connected to each die by fusible elements, biasing the dice using said conductors during the high temperature burn-in, testing the fusible elements, removing the conductors, and testing the circuits.

DETAILED DESCRIPTION An object of the present invention is to provide a method of preparing the dice on a substrate for biased test qualification at the wafer level.
A further object of the invention is to provide protection of integrated circuits from shorted integrated circuits during the biasing required for a given environmental qualification.
An even further object of the present invention is to provide means for biasing the plurality of integrated circuits on a wafer which is compatible with the integrated circuit fabrication process and which diminishes minimally the surface area available for integrated circuits.
Another object is to provide a test procedure for biased burn-in qualification on the wafer level.
These and other objects of the invention are attained by forming two sets of conductors on the wafer over the scribe line connected to each die.
At least one fusible element connects each die to at least one set of conductors.
Each of the dice are biased by a voltage applied to a pair of terminals for the two sets of conductors and the wafer is subjected to a qualifying environment during the biasing period.
Subsequent to the exposure to the qualifying environments, the fusible elements are tested to determine if they were either initially defective or if they had been blown during biasing, and the disconnected dice are marked.
Prior to the circuit testing, the sets of conductors are removed from the wafer as well as the underlying insulative layer to expose the areas in which the wafer is to be scribed.
The circuits are then individually tested and marked.
The scribed wafer is broken into a plurality of dice and the unmarked dice or qualified integrated circuits are separated from the marked or disqualified dice.
The qualified integrated circuits are then assembled into appropriate housings.
For a biased burn-in environment, the wafer is subjected to a high temperature burn-in for an extended period of time, for example, 168 hours during biasing.



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