Method for wafer scale testing of redundant integrated circuit dies

DETAILED DESCRIPTION The present invention provides an improved system and method for testing redundant integrated circuit dies formed on a semiconductor wafer.
The test system and method of the present invention provides relatively fast and low cost testing of integrated circuit dies.
Furthermore, the test system and method of the present invention is suitable for low noise testing in extreme environments such as testing under cryogenic conditions.
In a preferred embodiment, the present invention provides a wafer scale testing system and method which is employed in conjunction with redundant integrated circuit dies fabricated on a semiconductor wafer.
The individual integrated circuit dies include conventional electrical bonding pads and are each separated by dicing lanes for subsequent sawing and separation of the individual integrated circuit dies.
The wafer scale testing system preferably includes a single set of wafer test pads provided on the semiconductor wafer.
The wafer test pads are connected to the individual integrated circuit dies through an interchip multiplexor system.
The interchip multiplexor system enables individual integrated circuit dies on the wafer to be addressed from the wafer test pads and provided with electrical test signals and allows electrical test output signals therefrom to be read out.
In a preferred embodiment, the interchip multiplexor system includes an input/output multiplexor circuit for converting signals applied to the wafer test pads to test signals applied to the individual integrated circuit dies.
The interchip multiplexor system further includes interchip multiplexor lines for routing the signals to and from the individual integrated circuit dies.
In a preferred embodiment, the interchip multiplexor lines include a chip select bus and a test connect bus for selecting the individual dies for testing and supplying test signals to the selected die, respectively.
The interchip multiplexor lines are of necessity connected to the dies by leads which run over the dicing lanes on the semiconductor wafer