Microprocessor breakpoint apparatus

DETAILED DESCRIPTION The present invention provides a breakpoint signal apparatus useful in debugging computer programs.
The apparatus is particularly useful in an integrated circuit microprocessor formed on a single substrate which includes address generation means for generating virtual addresses for reference to program instructions or data, a virtual address bus, address translation means for converting the virtual address on the bus to a physical address, interpretation means for interpreting the program instructions, and arithmetic means for operating upon the data in accordance with the interpreted instructions.
The apparatus includes a first register for storing a predetermined address in the form of a virtual address at which a breakpoint is to occur.
A second register is used for storing control bits which permit the user to select certain conditions of the breakpoint such as whether the breakpoint is to occur at a reference to computer program or data.
A comparator means compares the predetermined virtual address with the address generated by the computer (current virtual address).
A first logic means determines if the current virtual address is a reference to program instructions or data by examining address control signals.
This logic means is also controlled by the control bits stored in the second register.
Gating means used to provide the breakpoint signal and interrupt the operation of the computer is coupled to the output of the comparator means and the first logic means.
The entire apparatus is formed on the same substrate with the microprocessor.
The apparatus also includes second logic means to determine if the current virtual address falls within the reference represented by the predetermined address or if the reference represented by the predetermined address falls within the reference made by the virtual address.
In effect, this permits the width of the of the predetermined breakpoint address to be set by control bits stored in the second register.