Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home Processing Data Module-and-a-substrate-for-the-module

 Main memory system and checkpointing protocol for a fault-tolerant computer system using a read buffer
Embodiments of the present invention provide a main memory device and a process for maintaining, in ...


 Interrupts between asynchronously operating CPUs in fault tolerant computer system
In accordance with one embodiment of the invention, a computer system employs three identical CPUs ...


 Memory processing system and method for accessing memory including reordering memory requests to reduce mode switching
In accordance with the present invention, memory accesses are reordered to improve efficiency. A ...


 Method and apparatus for snoop stretching using signals that convey snoop results
The present invention provides a protocol and related apparatus for snoop stretching in a computer ...


 Module and a substrate for the module

Details
Inventors: Matsumoto, Kunio; Noro, Takanobu; Kanda, Naoya;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Envall, Jr.; Roy N.
Assistant Examiner:
Attorney, Agent or Firm: Antonelli, Terry & Wands

This invention relates to a module which mounts a plurality of semiconductor devices and to a module substrate that interconnect the semiconductor devices. This invention has the testing and engineering change pads on the underside of the substrate. This arrangement results in the advantages of: providing a sufficient area for the testing and engineering change pads; improving the package density of semiconductor devices, which in turn leads to higher computation speed; and eliminating the need for a special cooling system during the module testing, simplifying the process of testing. Furthermore, since the signal joint terminals to the semiconductor chips are provided on the surface of the substrate on which the semiconductor chips are mounted and since the power bus joint terminals are provided around the chips on the semiconductor chip-mounting surface of the substrate, it is possible to realize a high density package with high reliability.

DETAILED DESCRIPTION A primary object of the present invention is to provide a module and a module substrate used for the module, which clear two problems (1) reduced chip package density resulting from securing an area for the testing and engineering pads; and (2) the necessity of using a cooling system for module testing.
A second object of the invention is to provide a module that can (1) improve the cooling ability and (2) accommodate an increased number of joints and thereby improve the bonding efficiency.
The first object can be achieved in the present invention by providing the testing and engineering change pads on the underside of the substrate.
By placing on the underside of the substrate the testing and engineering change pads that have conventionally been arranged on the chip-mounting surface of the substrate around the periphery of the LSI chip, an area available for the pads increases by as much as the chip-mounting area, allowing an increased number of testing and engineering change pads to be accommodated.
This makes it possible to mount the LSI chips with greater density while securing a sufficient number of testing and engineering change pads.
Another advantage is that during module testing, the testing probe can be connected to the testing and engineering change pads from the underside of the substrate, which eliminates the need to remove the cooling means thermal-joined to the back of the chips and therefore requires no special cooling system for testing.
The second object is achieved in the present invention by placing input/output joint terminals to the semiconductor chips on the chip-mounting surface of the substrate and by arranging power bus joint terminals around the chips on the chip-mounting surface of the substrate.
The arrangement of the power bus joint terminals around the chips on the chip-mounting surface of the substrate allows the underside to be used only for input/output joints, which increases the joint-to-joint space thereby improving the bonding efficiency



Related patents
  Low-cost power device package with quick-connect terminals and electrically isolated mounting means
The attainment of the foregoing and other objectives and advantages, is achieved through the present invention wherein a prepackaged semiconductor device having an ...
  Integrated circuit package with low-thermal expansion lead pieces
The object of the present invention is to provide an integrated circuit package which is capable of preventing the glass layer from being cracked thereby maintaining ...
  Beam index color cathode ray tube with color-identifying patterns of stripes disposed in beam run-in area of display surface
What is claimed is: 1. A television receiver characterized in that a plurality of image-displaying fluorescent lines are disposed on a display surface of a cathode ray ...
  Method and apparatus for displaying an enlarged image on multiple monitors to form a composite image
What is claimed is: 1. A method for displaying an image from video signals, comprising the steps of: generating video signals indicative of an interlaced image, said ...
  Sonar flasher speed control
This and other objects are realized and the limitations of the prior art are overcome in this invention by utilizing the first electrical pulse, which is used to ...
  Hybrid write back/write through cache having a streamlined four state cache coherency protocol for uniprocessor computer systems
Under the present invention, the desired results are advantageously achieved by providing the cache controller of a hybrid write back/write through cache of an ...
  Method and apparatus to control cache memory in multiprocessor system utilizing a shared memory
It is an object of the present invention to provide a cache memory control method which is suitable for all kinds of software architectures. It is another object of the ...
  Method and system for efficient maintenance of data coherency in a multiprocessor system utilizing cache synchronization
It is therefore one object of the present invention to provide enhanced data coherency in a data processing system. It is another object of the present invention to ...
  Dynamic mechanism to upgrade o state memory-consistent cache lines
In view of the above and other shortcomings in the art recognized by the present invention, the present invention introduces an O cache consistency state that permits ...
  Non-volatile semiconductor memory capable of readily erasing data
Therefore, one object of the present invention is to provide a non-volatile semiconductor memory in which the area occupied by one memory cell can be reduced. Another ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved